A robust speech recognition system using frm running spectrum filtering

Author(s):  
N. Hayasaka ◽  
N. Wada ◽  
S. Yoshizawa ◽  
Y. Miyanaga
2010 ◽  
Author(s):  
Gökhan Ince ◽  
Kazuhiro Nakadai ◽  
Tobias Rodemann ◽  
Hiroshi Tsujino ◽  
Jun-ichi Imura

2005 ◽  
Vol 17 (4) ◽  
pp. 447-455 ◽  
Author(s):  
Shingo Yoshizawa ◽  
◽  
Noboru Hayasaka ◽  
Naoya Wada ◽  
Yoshikazu Miyanaga

This paper presents a VLSI architecture for a robust speech recognition system that enables high-speed, low-power operation. The proposed architecture improves recognition accuracy in noisy environments and realizes short-time response by implementing parallel and pipeline processing. We demonstrate improved processing time and power consumption by evaluating circuit performance in 0.25-μm CMOS technology. We also detail a verification platform that helps users implement our hardware-based robust speech recognition system. The verification platform facilitates software conversion to hardware and promptly provides testing environments on field-programmable gate arrays.


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