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Area Efficient Built-In Redundancy Analysis using Pre-Solutions with Various Spare Structure
Mapping Intimacies
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10.1109/isocc53507.2021.9613937
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2021
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Author(s):
Youngki Moon
◽
Hyunho Yoo
◽
Donghyun Han
◽
Sungho Kang
Keyword(s):
Redundancy Analysis
◽
Area Efficient
Download Full-text
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Cited By
References
An Area Efficient Built-In Redundancy Analysis for Embedded Memory with Selectable 1-D Redundancy
Advances in Intelligent Systems and Computing - Intelligent Systems Technologies and Applications 2016
◽
10.1007/978-3-319-47952-1_58
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2016
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pp. 721-728
Author(s):
Gurugubelli Srirama Murthy
◽
Darvinder Singh
◽
Sadulla Shaik
Keyword(s):
Redundancy Analysis
◽
Embedded Memory
◽
Area Efficient
Download Full-text
An area-efficient built-in redundancy analysis for embedded memories with optimal repair rate using 2-D redundancy
2009 International SoC Design Conference (ISOCC)
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10.1109/socdc.2009.5423846
◽
2009
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Author(s):
Joohwan Lee
◽
Kihyun Park
◽
Sungho Kang
Keyword(s):
Redundancy Analysis
◽
Repair Rate
◽
Embedded Memories
◽
Area Efficient
Download Full-text
Design of an Area-Efficient and Low-Power Hierarchical NoC Architecture Based on Circuit Switching
IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences
◽
10.1587/transfun.e92.a.890
◽
2009
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Vol E92-A
(3)
◽
pp. 890-899
Author(s):
Woo Joo KIM
◽
Sung Hee LEE
◽
Sun Young HWANG
Keyword(s):
Low Power
◽
Circuit Switching
◽
Area Efficient
Download Full-text
Low-Power and Area-Efficient Approximate Parallel Design Using Bypassing
SSRN Electronic Journal
◽
10.2139/ssrn.3428931
◽
2019
◽
Cited By ~ 1
Author(s):
Anushka Prakash B
◽
Noah Kiran Nandi
◽
Marimuthu R
◽
Balamurugan S
◽
Duraivel A.N.
Keyword(s):
Low Power
◽
Parallel Design
◽
Area Efficient
Download Full-text
VLSI Implementation of High Speed-Low Power-Area Efficient Multiplier Using Modified Vedic Mathematical Techniques
Recent Patents on Computer Science
◽
10.2174/2213275908666150220203501
◽
2017
◽
Vol 9
(3)
◽
pp. 216-221
Author(s):
Abdul Kareem
◽
Vardhana M.
◽
Praveen Kumar
Keyword(s):
Low Power
◽
High Speed
◽
Vlsi Implementation
◽
Mathematical Techniques
◽
Area Efficient
Download Full-text
Energy and Area Efficient 11-T Ternary Content Addressable Memory for High-Speed Search
2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)
◽
10.1109/edssc.2019.8754423
◽
2019
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Author(s):
Diptesh Datta
◽
Piyush Dewangan
◽
Neelam Surana
◽
Joycee Mekie
Keyword(s):
High Speed
◽
Content Addressable Memory
◽
Ternary Content Addressable Memory
◽
Area Efficient
Download Full-text
Area Efficient Approximate 4–2 Compressor for Multiplier Design
2020 IEEE India Council International Subsections Conference (INDISCON)
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10.1109/indiscon50162.2020.00055
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2020
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Author(s):
Chinthalgiri Jyothi
◽
Kuruva Gayathri
◽
Saranya Karunamurthi
◽
Sreehari Veeramachaneni
◽
Noor Mahammad S
Keyword(s):
Area Efficient
Download Full-text
Comparison Of Capacitive DAC Architectures for Power and Area Efficient SAR ADC Designs
2021 IEEE International Symposium on Circuits and Systems (ISCAS)
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10.1109/iscas51556.2021.9401768
◽
2021
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Author(s):
Ankita Ahuja
◽
Komail Badami
◽
Cedric Barbelenet
◽
Stephane Emery
Keyword(s):
Sar Adc
◽
Capacitive Dac
◽
Area Efficient
Download Full-text
A Self-Powered and Area Efficient SSHI Rectifier for Piezoelectric Harvesters
IEEE Access
◽
10.1109/access.2021.3107365
◽
2021
◽
Vol 9
◽
pp. 117703-117713
◽
Cited By ~ 1
Author(s):
Salar Chamanian
◽
Berkay Ciftci
◽
Ali Muhtaroglu
◽
Haluk Kulah
Keyword(s):
Self Powered
◽
Area Efficient
Download Full-text
Area-Efficient Extended 3-D Inductor Based on TSV Technology for RF Applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
◽
10.1109/tvlsi.2020.3036385
◽
2020
◽
pp. 1-10
Author(s):
Chenbing Qu
◽
Zhangming Zhu
◽
Yunfei En
◽
Liwei Wang
◽
Xiaoxian Liu
Keyword(s):
Rf Applications
◽
Area Efficient
Download Full-text
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