Embedded Memories for Cryogenic Applications

The ever-growing interest in cryogenic applications has prompted the investigation for energy-efficient and high-density memory technologies that are able to operate efficiently at extremely low temperatures. This work analyzes three appealing embedded memory technologies under cooling—from room temperature (300 K) down to cryogenic levels (77 K). As the temperature goes down to 77 K, six-transistor static random-access memory (6T-SRAM) presents slight improvements for static noise margin (SNM) during hold and read operations, while suffering from lower (−16%) write SNM. Gain-cell embedded DRAM (GC-eDRAM) shows significant benefits under these conditions, with read voltage margins and data retention time improved by about 2× and 900×, respectively. Non-volatile spin-transfer torque magnetic random access memory (STT-MRAM) based on single- or double-barrier magnetic tunnel junctions (MTJs) exhibit higher read voltage sensing margins (36% and 48%, respectively), at the cost of longer write access time (1.45× and 2.1×, respectively). The above characteristics make the considered memory technologies to be attractive candidates not only for high-performance computing, but also enable the possibility to bridge the gap from room-temperature to the realm of cryogenic applications that operate down to liquid helium temperatures and below.

Mutual Recognition: Empathy as the Foundation of Community in Dementia

This paper explores the challenges of developing a healthy, genuine community as some of its members experience cognitive decline or dementia. I draw upon philosophical discussions on community (Stein, 2000) and Husserlian empathy (1931;1939) to identify these challenges. First, community is organic; it relies on the differentiated roles of individual members to remain healthy. The ability to recognize the contribution of each member is essential for its health. Second, dyadic relationships may similarly be healthy or waning depending on the presence or absence of mutual empathy. Empathy is embodied. Persons living with dementia (PLWD) need to experience being recognized as persons, in person, in order for dyadic relationships and communities to thrive. As such, some communities may become unhealthy in the absence of mutual recognition. In these instances, careful interventions, e.g., through shared experiences and embedded memories, may be required to promote the well-being of the community and its members.

A review paper on memory fault models and test algorithms

Testing embedded memories in a chip can be very challenging due to their high-density nature and manufactured using very deep submicron (VDSM) technologies. In this review paper, functional fault models which may exist in the memory are described, in terms of their definition and detection requirement. Several memory testing algorithms that are used in memory built-in self-test (BIST) are discussed, in terms of test operation sequences, fault detection ability, and also test complexity. From the studies, it shows that tests with 22 N of complexity such as March SS and March AB are needed to detect all static unlinked or simple faults within the memory cells. The N in the algorithm complexity refers to Nx*Ny*Nz whereby Nx represents the number of rows, Ny represents the number of columns and Nz represents the number of banks. This paper also looks into optimization and further improvement that can be achieved on existing March test algorithms to increase the fault coverage or to reduce the test complexity.

High-Throughput Calculations on the Decomposition Reactions of Off-Stoichiometry GeSbTe Alloys for Embedded Memories

Chalcogenide GeSbTe (GST) alloys are exploited as phase change materials in a variety of applications ranging from electronic non-volatile memories to neuromorphic and photonic devices. In most applications, the prototypical Ge2Sb2Te5 compound along the GeTe-Sb2Te3 pseudobinary line is used. Ge-rich GST alloys, off the pseudobinary tie-line with a crystallization temperature higher than that of Ge2Sb2Te5, are currently explored for embedded phase-change memories of interest for automotive applications. During crystallization, Ge-rich GST alloys undergo a phase separation into pure Ge and less Ge-rich alloys. The detailed mechanisms underlying this transformation are, however, largely unknown. In this work, we performed high-throughput calculations based on Density Functional Theory (DFT) to uncover the most favorable decomposition pathways of Ge-rich GST alloys. The knowledge of the DFT formation energy of all GST alloys in the central part of the Ge-Sb-Te ternary phase diagram allowed us to identify the cubic crystalline phases that are more likely to form during the crystallization of a generic GST alloy. This scheme is exemplified by drawing a decomposition map for alloys on the Ge-Ge1Sb2Te4 tie-line. A map of decomposition propensity is also constructed, which suggests a possible strategy to minimize phase separation by still keeping a high crystallization temperature.

Optimal Method for Test and Repair Memories Using Redundancy Mechanism for SoC

The current system-on-chip (SoC)-based devices uses embedded memories of enormous size. Most of these systems’ area is dense with memories and promotes different types of faults appearance in memory. The memory faults become a severe issue when they affect the yield of the product. A memory-test and -repair scheme is an attractive solution to tackle this kind of problem. The built-in self-repair (BISR) scheme is a prominent method to handle this issue. The BISR scheme is widely used to repair the defective memories for an SoC-based system. It uses a built-in redundancy analysis (BIRA) circuit to allocate the redundancy when defects appear in the memory. The data are accessed from the redundancy allocation when the faulty memory is operative. Thus, this BIRA scheme affects the area overhead for the BISR circuit when it integrates to the SoC. The spare row and spare column–based BISR method is proposed to receive the optimal repair rate with a low area overhead. It tests the memories for almost all the fault types and repairs the memory by using spare rows and columns. The proposed BISR block’s performance was measured for the optimal repair rate and the area overhead. The area overhead, timing, and repair rate were compared with the other approaches. Furthermore, the study noticed that the repair rate and area overhead would increase by increasing the spare-row/column allocation.

Improvement of Fault Tolerance in Smart Sensors using Roll Back and Parity Check

Background and Objective: Fault-tolerant IoT (Internet of Things) architecture is the need of the hour when we foresee major developments in this sector. Fault tolerance can be established at various levels. IoT devices require faulttolerant smart sensors. Coping with soft and hard faults in a smart sensor is a challenging task. In the past, the extensive efforts for fault tolerance were associated with on-chip memories. Method: To detect the error in logic functions, numerous solutions already exist, but only a few of them allow the correction, which leads to an increase in overhead of hardware in non-processor design. In this paper fault tolerance in onchip memories of the smart sensor is implemented using rollback mechanisms parity generator and checker using Xilinx ISE. Results: Improved fault tolerance in embedded memories. Conclusion: The rollback and parity check method is found effective in ensuring fault tolerance in embedded memories.

Lightweight Software-Defined Error Correction for Memories

Reliability of the memory subsystem is a growing concern in computer architecture and system design. From on-chip embedded memories in Internet-of-Things (IoT) devices and on-chip caches to off-chip main memories, the memory subsystems have become the limiting factor in the overall reliability of computing systems. This is because they are primarily designed to maximize bit storage density; this makes memories particularly sensitive to manufacturing process variation, environmental operating conditions, and aging-induced wearout. This chapter of the book focuses on software managed techniques and novel error correction codes to opportunistically cope with memory errors whenever they occur for improved reliability at minimal cost.