High-performance noise tolerant comparator design for arithmetic circuits

2016 ◽  
Author(s):  
Preetisudha Meher ◽  
Kamala Kanta Mahapatra
Keyword(s):  
High Performance ◽  
Arithmetic Circuits ◽  
Noise Tolerant

A Novel Low Power Noise Tolerant High Performance Dynamic Feed through Logic Design Technique

2011 ◽  
Author(s):  
Manisha Pattanaik ◽  
Shashank Parashar ◽  
Chaudhry Indra Kumar ◽  
Akanksha Chouhan ◽  
Vikas Mahor
Keyword(s):  
Low Power ◽  
High Performance ◽  
Logic Design ◽  
Design Technique ◽  
Power Noise ◽  
Noise Tolerant

Skewed CMOS: noise-tolerant high-performance low-power static circuit family

2002 ◽  
Vol 10 (4) ◽  
pp. 469-476 ◽  
Author(s):  
A. Solomatnikov ◽  
D. Somasekhar ◽  
N. Sirisantana ◽  
K. Roy
Keyword(s):  
Low Power ◽  
High Performance ◽  
Noise Tolerant ◽  
Circuit Family

scholarly journals A New Ultra Low-Power and Noise Tolerant Circuit Technique for CMOS Domino Logic

2013 ◽  
pp. 177-182
Author(s):  
Preetisudha Meher ◽  
K. K. Mahapatra
Keyword(s):  
High Performance ◽  
Dynamic Logic ◽  
Charge Sharing ◽  
Cmos Inverter ◽  
Small Noise ◽  
Domino Logic ◽  
Ultra Low Power ◽  
Noise Tolerant ◽  
Power Delay Product ◽  
Circuit Technique

Dynamic logic style is used in high performance circuit design because of its fast speed and less transistors requirement as compared to CMOS logic style. But it is not widely accepted for all types of circuit implementations due to its less noise tolerance and charge sharing problems. A small noise at the input of the dynamic logic can change the desired output. Domino logic uses one static CMOS inverter at the output of dynamic node which is more noise immune and consuming very less power as compared to other proposed circuit. In this paper we have proposed a novel circuit for domino logic which has less noise at the output node and has very less power-delay product (PDP) as compared to previous reported articles. Low PDP is achieved by using semi-dynamic logic buffer and also reducing leakage current when PDN is not conducting.

Mixed Full Adder topologies for high-performance low-power arithmetic circuits

2007 ◽  
Vol 38 (1) ◽  
pp. 130-139 ◽  
Author(s):  
M. Alioto ◽  
G. Di Cataldo ◽  
G. Palumbo
Keyword(s):  
Low Power ◽  
High Performance ◽  
Full Adder ◽  
Arithmetic Circuits

High-performance noise-tolerant circuit techniques for CMOS dynamic logic

2008 ◽  
Vol 2 (6) ◽  
pp. 537 ◽  
Author(s):  
F. Frustaci ◽  
P. Corsonello ◽  
S. Perri ◽  
G. Cocorullo
Keyword(s):  
High Performance ◽  
Dynamic Logic ◽  
Circuit Techniques ◽  
Noise Tolerant

Educational design of high-performance arithmetic circuits on FPGA

1999 ◽  
Vol 42 (4 [+CDROM]) ◽  
pp. 27 pp. ◽  
Author(s):  
G. Cappuccino ◽  
G. Cocorullo ◽  
P. Corsonello ◽  
S. Perri
Keyword(s):  
High Performance ◽  
Arithmetic Circuits ◽  
Educational Design

A High-Performance and Energy-Efficient FIR Adaptive Filter Using Approximate Distributed Arithmetic Circuits

2019 ◽  
Vol 66 (1) ◽  
pp. 313-326 ◽  
Author(s):  
Honglan Jiang ◽  
Leibo Liu ◽  
Pieter P. Jonker ◽  
Duncan G. Elliott ◽  
Fabrizio Lombardi ◽  
...  
Keyword(s):  
Adaptive Filter ◽  
Energy Efficient ◽  
High Performance ◽  
Arithmetic Circuits ◽  
Distributed Arithmetic
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