Low Power Adiabetic Logic System for Biomedical Applications

There have been significant advances in sensors and device structures in the medical industry, particularly in implanted medical devices. Increasingly complex electronic circuitry may now be implanted in the human body thanks to compact, high-energy batteries and hermetic packaging. These gadgets must adhere to strict power consumption guidelines due to the battery recharging schedule. Designing energy-efficient circuits and systems becomes increasingly important as a result of this fact. Adiabatic circuits provide a hopeful alternative for traditional circuitry in case of low energy design. Because of power-clock phases synchronization complexity, designing and functionally verifying presenting 4-phase adiabatic circuitry takes longer. Accordingly, multiple clock generators are used typically and can reveal enhanced consumption of energy in the network of clock distribution. Furthermore, they are not suitable for designing in high-speed because of their clock skew management and high complexity issues. In this paper, TMEL (True multi-phase energy recovering logic), the first energyrecovering/adiabatic logic family is presented for biomedical applications, which functions using the scheme multiple-phase sinusoidal clocking. Moreover, a system of SCAL, a source-coupled variation with TMEL having enhanced energy efficiency and supply voltage scalability, is introduced. A novel true multi-phase Approach and Source-coupled adiabatic logic for energy effective communication system is proposed. The adiabatic logic is employed for both write and read side operation. The CMOS inverter is integrated with TMEL cascades, which in turn reduces leakage loss. In SCAL, the optimal performance at any operating circumstance is attained byan adjustable current source in each gate. SCAL, and TMEL, are capable of outperforming existing adiabatic logic families concerning operating speed and energy efficiency. The performance analysis was carried and simulated through 45 nm CMOS inverter in terms of leakage power, delay, and power consumption. In particular, for the clock rates that range from 10 MHz to 200 MHz, the proposed SCAL was more energy-efficient and less dissipative on comparing their pipelined or purely combinational CMOS counterparts. In biomedical equipment, the system may be included into the low-power design since it is energy efficient and very robust. Improvements in VLSI technology, such as increased dynamic range, low-voltage EEPROMs (electrically eraseable programmable ROMs), and specific sensor techniques, are also expected to contribute to advancements in implanted medical devices in the near future.

p-Type Trigate Junctionless Nanosheet MOSFET: Analog/RF, Linearity, and Circuit Analysis

Silicon (Si) nanosheet (NS) metal-oxide semiconductor field effect transistors (MOSFETs) are realized as an outstanding structure to obtain better area scaling and power performance compared to FinFETs. Si NS MOSFETs provide high current drivability due to wider effective channel (Weff) and maintain better short channel performance. Here, the performance of junctionless (JL) NS p-MOSFET was evaluated by invoking HfxTi1-xO2 gate stack. The device performance was enhanced using various spacer dielectrics and the electrical characteristics are presented. Moreover, the effect of NS width variation on ION/IOFF, SS, Vth is presented and the analog/RF metrics of the device are evaluated. The power analysis of NS MOSFET is presented with respect to the ITRS road map. Our investigation reveals that the device exhibits an ION/IOFF ratio of more than ~106 with NS widths of 10 to 30 nm, respectively. For high-performance applications, the device exhibits better performance (ION) with higher NS widths. However, the threshold voltage downfall leads to deterioration in subthreshold performance with an increase in NS widths. With Si3N4 as a spacer dielectric the device exhibits better static power consumption for the CMOS inverter. By careful control of NS width and effective usage of spacer dielectric ensures better p-MOSFET design for future technology nodes.

Experimental demonstration of high-gain CMOS inverter operation at low Vdd down to 0.5 V consisting of WSe2 n/p FETs

In this paper, we report on the device concepts for high-gain operation of a tungsten diselenide (WSe2) complementary metal-oxide-semiconductor (CMOS) inverter at a low power supply voltage (Vdd), which was realized by developing a doping technique and gate stack technology. A spin-coating with a fluoropolymer and poly(vinyl alcohol) (PVA) results in the doping of both electrons and holes to WSe2. A hybrid self-assembled monolayer (SAM)/aluminum oxide (AlOx) gate dielectric is viable for achieving high gate capacitance and superior interfacial properties. By developing the doping technique and gate stack technology, we experimentally realized a high gain of 9 at Vdd of 0.5 V in the WSe2 CMOS inverter. This study paves the way for the research and development of transition metal dichalcogenides (TMDC)-based devices and circuits.

Circuit Analysis and Optimization of GAA Nanowire FET Towards Low Power and High Switching

The main aim of this work is to study the effect of symmetric and asymmetric spacer length variations towards source and drain on n-channel SOI JL vertically stacked (VS) nanowire (NW) FET at 10 nm gate length (LG). Spacer length is proved to be one of the stringent metrics in deciding device performance along with width, height and aspect ratio (AR). The physical variants in this work are symmetric spacer length (LSD), source side spacer length (LS) and drain side spacer length (LD). The simulation results give highest ION/IOFF ratio with LD variation compared to LS and LSD, whereas latter two variations have similar effect on ION/IOFF ratio. At 25 nm (2.5 × LG) of LD, the device gives appreciable ON current with the highest ION/IOFF ratio (2.19 × 108) with optimum subthreshold slope (SS) and ensures low power and high switching drivability. Moreover, it is noticed that among optimal values of LS and LD, the device ION/IOFF ratio has an improvement of 22.69% as compared to other variations. Moreover, the effect of various spacer dielectrics on optimized device is also investigated. Finally, the CMOS inverter circuit analysis is performed on the optimized symmetric and asymmetric spacer lengths.

Design and Characteristics of CMOS Inverter based on Multisim and Cadence

Known as complementary symmetrical metal oxide semiconductor (cos-mos), complementary metal oxide semiconductor is a metal oxide semiconductor field effect transistor (MOSFET) manufacturing process, which uses complementary and symmetrical pairs of p-type and n-type MOSFETs to realize logic functions. CMOS technology is used to build integrated circuit (IC) chips, including microprocessors, microcontrollers, memory chips (including CMOS BIOS) and other digital logic circuits. CMOS technology is also used in analog circuits, such as image sensors (CMOS sensors), data converters, RF circuits (RF CMOS), and highly integrated transceivers for various types of communications. Based on multisim 14.0 and cadence, the characteristics and performance of CMOS inverter are studied by simulation.

Low-power 25Gb/s 16:1 Multiplexer for 400Gb/s Ethernet PHY

A lower power 25Gb/s 16:1 multiplexer using 65nm CMOS technology for 400Gb/s Ethernet (400GbE) physical layer (PHY) interface was presented. CMOS+CML mixed logic is adopted to achieve hierarchical architecture, avoiding the high clock requirement of one-step structure and improving the transmission speed. In order to reduce power while achieving high data rate, multiplexing structure is also optimized by utilizing multi-frequency multi-phase technology which not only ensures the requirement of the phase stabilization, but also leaves out some flip-flops. For CMOS-CML conversion circuit, transmission gate and cross-coupled CMOS inverter are used to match the delay of CMOS inverter, suppressing the effect of common-mode noise. Simulation results show that the multiplexer works correctly and jitter of output signal is less than 0.1UI. When voltage is 1.2V, the total power is 32.7mW at 25Gb/s.