Flush-Reload Attack and its Mitigation on an FPGA Based Compressed Cache Design

2021 22nd International Symposium on Quality Electronic Design (ISQED) ◽

10.1109/isqed51717.2021.9424252 ◽

2021 ◽

Author(s):

Prashant Mata ◽

Nanditha Rao

Keyword(s):

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A low energy cache design for multimedia applications exploiting set access locality

Journal of Systems Architecture ◽

10.1016/j.sysarc.2005.02.003 ◽

2005 ◽

Vol 51 (10-11) ◽

pp. 653-664 ◽

Author(s):

Jun Yang ◽

Jia Yu ◽

Youtao Zhang

Keyword(s):

Multimedia Applications ◽

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Early resolution of address translation in cache design

Proceedings., 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors ◽

10.1109/iccd.1990.130264 ◽

2002 ◽

Author(s):

K. Hua ◽

A. Hunt ◽

L. Liu ◽

J.-K. Peir ◽

D. Pruett ◽

...

Keyword(s):

Address Translation ◽

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Content hunting for in-network cache: Design and performance analysis

2014 IEEE International Conference on Communications (ICC) ◽

10.1109/icc.2014.6883809 ◽

2014 ◽

Author(s):

Hiroshi Shimizu ◽

Hitoshi Asaeda ◽

Masahiro Jibiki ◽

Nozomu Nishinaga

Keyword(s):

Performance Analysis ◽

And Performance ◽

Network Cache ◽

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Low-Power Cache Design

Low-Power Electronics Design ◽

10.1201/9781420039559-32 ◽

2018 ◽

pp. 455-476

Keyword(s):

Low Power ◽

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Efficient cache design for solid-state drives

Proceedings of the 7th ACM international conference on Computing frontiers - CF '10 ◽

10.1145/1787275.1787282 ◽

2010 ◽

Author(s):

Miaoqing Huang ◽

Olivier Serres ◽

Vikram K. Narayana ◽

Tarek El-Ghazawi ◽

Gregory Newby

Keyword(s):

Solid State ◽

Solid State Drives ◽

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A Hybrid Non-Volatile Cache Design for Solid-State Drives Using Comprehensive I/O Characterization

IEEE Transactions on Computers ◽

10.1109/tc.2015.2455978 ◽

2016 ◽

Vol 65 (6) ◽

pp. 1678-1691 ◽

Author(s):

Mojtaba Tarihi ◽

Hossein Asadi ◽

Alireza Haghdoost ◽

Mohammad Arjomand ◽

Hamid Sarbazi-Azad

Keyword(s):

Solid State ◽

Solid State Drives ◽

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Reliable Ultra-Low-Voltage Cache Design for Many-Core Systems

IEEE Transactions on Circuits & Systems II Express Briefs ◽

10.1109/tcsii.2012.2231013 ◽

2012 ◽

Vol 59 (12) ◽

pp. 858-862 ◽

Author(s):

Meilin Zhang ◽

Vladimir M. Stojanovic ◽

Paul Ampadu

Keyword(s):

Low Voltage ◽

Many Core ◽

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Cache Design for Yield-per-Area Maximization: Switchable Spare Columns with Disabling (SSC-Disable)

2019 IEEE 37th VLSI Test Symposium (VTS) ◽

10.1109/vts.2019.8758652 ◽

2019 ◽

Author(s):

Soowang Park ◽

Sandeep K. Gupta

Keyword(s):

Cache Design ◽

Design For Yield

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First-Level Instruction Cache Design for Reducing Dynamic Energy Consumption

Lecture Notes in Computer Science - Embedded Computer Systems: Architectures, Modeling, and Simulation ◽

10.1007/11512622_12 ◽

2005 ◽

pp. 103-111 ◽

Author(s):

Cheol Hong Kim ◽

Sunghoon Shim ◽

Jong Wook Kwak ◽

Sung Woo Chung ◽

Chu Shik Jhon

Keyword(s):

Energy Consumption ◽

Instruction Cache ◽

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A switch cache design for MIN-based shared-memory multiprocessors

Parallel Processing: CONPAR 94 — VAPP VI - Lecture Notes in Computer Science ◽

10.1007/3-540-58430-7_38 ◽

1994 ◽

pp. 426-437

Author(s):

Mazin S. Yousif ◽

Chita R. Das

Keyword(s):

Shared Memory ◽

Shared Memory Multiprocessors ◽

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