Implementation of modeling and simulation in semiconductor wafer fabrication with time constraints between wet etch and furnace operations

1999 IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings (Cat No.99CH36314) ◽

10.1109/issm.1999.808738 ◽

2003 ◽

Author(s):

W. Scholl ◽

J. Domaschke

Keyword(s):

Modeling And Simulation ◽

Wafer Fabrication ◽

Time Constraints ◽

Semiconductor Wafer ◽

Semiconductor Wafer Fabrication ◽

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Implementation of modeling and simulation in semiconductor wafer fabrication with time constraints between wet etch and furnace operations

IEEE Transactions on Semiconductor Manufacturing ◽

10.1109/66.857935 ◽

2000 ◽

Vol 13 (3) ◽

pp. 273-277 ◽

Author(s):

W. Scholl ◽

J. Domaschke

Keyword(s):

Modeling And Simulation ◽

Wafer Fabrication ◽

Time Constraints ◽

Semiconductor Wafer ◽

Semiconductor Wafer Fabrication ◽

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Modeling and simulation of material handling for semiconductor wafer fabrication

Proceedings of Winter Simulation Conference ◽

10.1109/wsc.1994.717466 ◽

2005 ◽

Author(s):

N.G. Pierce ◽

R. Stafford

Keyword(s):

Modeling And Simulation ◽

Material Handling ◽

Wafer Fabrication ◽

Semiconductor Wafer ◽

Semiconductor Wafer Fabrication

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CAPACITY DETERMINATION MODEL WITH TIME CONSTRAINTS AND BATCH PROCESSING IN SEMICONDUCTOR WAFER FABRICATION

Journal of the Chinese Institute of Industrial Engineers ◽

10.1080/10170660609509008 ◽

2006 ◽

Vol 23 (3) ◽

pp. 192-199 ◽

Author(s):

Ying-Mei Tu ◽

Chuen-Shiuan Liou

Keyword(s):

Batch Processing ◽

Wafer Fabrication ◽

Time Constraints ◽

Semiconductor Wafer ◽

Semiconductor Wafer Fabrication ◽

Capacity Determination

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Capacity planning for semiconductor wafer fabrication with time constraints between operations

WSC'99. 1999 Winter Simulation Conference Proceedings. 'Simulation - A Bridge to the Future' (Cat. No.99CH37038) ◽

10.1145/324138.324545 ◽

1999 ◽

Author(s):

Jennifer K. Robinson ◽

Richard Giglio

Keyword(s):

Capacity Planning ◽

Wafer Fabrication ◽

Time Constraints ◽

Semiconductor Wafer ◽

Semiconductor Wafer Fabrication

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Dispatching rule considering time-constraints on processes for semiconductor wafer fabrication facility

2012 IEEE International Conference on Automation Science and Engineering (CASE) ◽

10.1109/coase.2012.6386370 ◽

2012 ◽

Author(s):

L. Li ◽

Y. F. Li ◽

Z. J. Sun

Keyword(s):

Wafer Fabrication ◽

Time Constraints ◽

Dispatching Rule ◽

Semiconductor Wafer ◽

Semiconductor Wafer Fabrication

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A generalized dispatching rule considering time-constraints on processes of a semiconductor wafer fabrication facility

2012 International Conference on System Simulation (ICUSS 2012) ◽

10.1049/cp.2012.0542 ◽

2012 ◽

Author(s):

Y.F. Li ◽

L. Li

Keyword(s):

Wafer Fabrication ◽

Time Constraints ◽

Dispatching Rule ◽

Semiconductor Wafer ◽

Semiconductor Wafer Fabrication

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Operational modeling and simulation of an inter-bay AMHS in semiconductor wafer fabrication

Proceedings of the Winter Simulation Conference ◽

10.1109/wsc.2002.1166405 ◽

2003 ◽

Author(s):

J. Jimenez ◽

B. Kim ◽

J. Fowler ◽

G. Mackulak ◽

You In Choung

Keyword(s):

Modeling And Simulation ◽

Wafer Fabrication ◽

Semiconductor Wafer ◽

Semiconductor Wafer Fabrication

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A performance model of automated material handling systems with double closed-loops and shortcuts in 300 mm semiconductor wafer fabrication systems

Journal of Manufacturing Systems ◽

10.1016/j.jmsy.2020.12.006 ◽

2021 ◽

Vol 58 ◽

pp. 316-334

Author(s):

Lihui Wu ◽

Zhongwei Zhang ◽

Jie Zhang ◽

Ray Y. Zhong ◽

Junliang Wang

Keyword(s):

Material Handling ◽

Performance Model ◽

Wafer Fabrication ◽

Semiconductor Wafer ◽

Closed Loops ◽

Material Handling Systems ◽

Semiconductor Wafer Fabrication ◽

Automated Material Handling ◽

Automated Material Handling Systems ◽

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Scheduling semiconductor wafer fabrication

IEEE Transactions on Semiconductor Manufacturing ◽

10.1109/66.4384 ◽

1988 ◽

Vol 1 (3) ◽

pp. 115-130 ◽

Author(s):

L.M. Wein

Keyword(s):

Wafer Fabrication ◽

Semiconductor Wafer ◽

Semiconductor Wafer Fabrication

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AN ANALYSIS OF DISPATCHING RULES IN A SEMICONDUCTOR WAFER FABRICATION ENVIRONMENT

Journal of Electronics Manufacturing ◽

10.1142/s0960313195000190 ◽

1995 ◽

Vol 05 (03) ◽

pp. 165-174 ◽

Author(s):

THOMAS McCUTCHEN ◽

CHUNG-YEE LEE

Keyword(s):

Wafer Fabrication ◽

Dispatching Rules ◽

Semiconductor Wafer ◽

Semiconductor Wafer Fabrication

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