Direct Conversion Receiver is the choice of the today’s designer for low power compact wireless receiver. DCR is attractive due to low power, small size and highly monolithic integratable structure, but distortions affect its performance. I/Q mismatch is the one of the major distortion which is responsible for performance degradation. In this paper, a novel method for Direct Conversion Receiver is suggested, which makes it insensitive to the I/Q mismatch. Here the classical homodyne architecture is modified to nullify effect of I/Q mismatch. The proposed method can be implemented in the Digital Signal Processing (DSP) back-end section also. This feature makes it acceptable in the already designed/functioning classical homodyne architecture based receiver.
Low Power Pipelined FFT Processor Architecture on FPGA