Machine Algorithm for Heartbeat Monitoring and Arrhythmia Detection Based on ECG Systems

Cardiac arrhythmia is an illness in which a heartbeat is erratic, either too slow or too rapid. It happens as a result of faulty electrical impulses that coordinate the heartbeats. Sudden cardiac death can occur as a result of certain serious arrhythmia disorders. As a result, the primary goal of electrocardiogram (ECG) investigation is to reliably perceive arrhythmias as life-threatening to provide a suitable therapy and save lives. ECG signals are waveforms that denote the electrical movement of the human heart (P, QRS, and T). The duration, structure, and distances between various peaks of each waveform are utilized to identify heart problems. The signals’ autoregressive (AR) analysis is then used to obtain a specific selection of signal features, the parameters of the AR signal model. Groups of retrieved AR characteristics for three various ECG kinds are cleanly separated in the training dataset, providing high connection classification and heart problem diagnosis to each ECG signal within the training dataset. A new technique based on two-event-related moving averages (TERMAs) and fractional Fourier transform (FFT) algorithms is suggested to better evaluate ECG signals. This study could help researchers examine the current state-of-the-art approaches employed in the detection of arrhythmia situations. The characteristic of our suggested machine learning approach is cross-database training and testing with improved characteristics.

A COMPARATIVE STUDY OF FFT ALGORITHMS FOR CONVOLUTION CALCULATION IN NON-PERIODIC ELASTIC CONTACTS

Department of Mechanics and Technologies, Stefan cel Mare University of Suceava; Integrated Center for Research, Development and Innovation in Advanced Materials, Nanotechnologies, and Distributed Systems for Fabrication and Control (MANSiD), Stefan cel Mare University, Suceava, Romania

Design of System Level Architecture of Multi-Core with Array Mapping Based on Floating Processing Factor-Fast Fourier Transform for Health Informatics Application

In FFT algorithms memory access patterns prevent multiple architectures from achieving high machine use, particularly when parallel processing is needed to achieve the desired efficiency rates. Beginning with the extremely powerful FFT heart, the on-chip memory hierarchy for the multicored FFT processor, is co-designed and linked on-chip. We have shown that the Floating Processing Factor (FPPE) proposed achieves greater operating rate and lower power for the application of health informatics. This test mechanism aids in omission of faulty cores and autonomous detection also makes elegant multi-core architecture degradation feasible. Experimental results illustrate that the anticipated design is scalable widely in terms of performance overhead and hardware overhead which makes it appropriate to many-cores with more than a thousand processing cores through Low Power and High Speed.

Iterative FFT-algorithms with high frequency resolution

В работе представлены три итерационных алгоритма быстрого преобразования Фурье с прореживанием по времени, имеющие алгоритмическую сложность O (N·R·log2N), где R — частотное разрешение спектральной характеристики (отношение длины набора частот к длине N набора отсчетов исходного сигнала). Алгоритмы отличаются способами организации вычислений: некоторые используют обратную перестановку битов, другие — дополнительные массивы. Приведены подробные вычислительные графы, а также блок-схемы разработанных алгоритмов. Полученные результаты можно использовать для улучшения отечественной электроники и программного обеспечения, а также включать в учебный процесс при подготовке инженеров в области цифровой обработки сигналов. This paper presents three iterative algorithms for fast Fourier transform with decimation in time; these algorithms have the algorithmic complexity O (N·R·log2N), where R is the frequency resolution of the spectral characteristic (the ratio of the length of the frequency set to the length of the N set of samples of the source signal). The algorithms differ in the way they organize calculations: some use reverse bit permutation, while the others use additional arrays. Detailed computational graphs and flowcharts of the developed algorithms are provided. The results obtained can be used to improve domestic electronics and software as well as may be included in the training process for engineers in the field of digital signal processing.

The fast Fourier transform

This chapter demonstrates the use of different data distributions in different phases of a parallel fast Fourier transform (FFT), which is a regular computation with a predictable but challenging data access pattern. Both the block and cyclic distributions are used and also intermediates between them. Each required data redistribution is a permutation that involves communication. By making careful choices, the number of such redistributions can be kept to a minimum. FFT algorithms can be concisely expressed using matrix/vector notation and Kronecker matrix products. This notation is also used here. The chapter then shows how permutations with a regular pattern can be implemented more efficiently by packing the data. The parallelization techniques discussed for the specific case of the FFT are also applicable to other related computations, for instance in signal processing and weather forecasting.

A 2048-point Split-Radix Fast Fourier Transform Computed using Radix-4 Butterfly Units

For the low-power consumption of fast fourier transform, Split-radix fast Fourier transforms are widely used. SRFFT uses less number of mathematical calculations amongst the different FFT algorithms. Split-radix FFT has the same signal flow graph that of conventional radix-2/4 FFT’s. Therefore, the address generation method is same for SRFFT as of radix-2. A low power SRFFT architecture with modified butterfly units is presented over here. Here, it is shown that the, a 2048-point SRFFT is computed using radix-4 butterfly unist. Dynamic power is saved, on compromising the use of extra hardware. Here, the architecture size is increased from radix-2 to 4 and the dynamic power consumption is evaluated.