Logical effort based design exploration of 64-bit adders using a mixed dynamic-CMOS/threshold-logic approach
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1974 ◽
Vol 37
(3)
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pp. 365-368
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2015 ◽
Vol 135
(7)
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pp. 893-900
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2017 ◽
Vol 12
(2)
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pp. 16
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2019 ◽
Vol 8
(3)
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pp. 5926-5929