IEEE Computer Society Annual Symposium on VLSI
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TOTAL DOCUMENTS

80

(FIVE YEARS 0)

H-INDEX

11

(FIVE YEARS 0)

Published By IEEE Comput. Soc

0769520979

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

The "4-diamond circuit" - a minimally complex nano-scale computational building block in QCA

IEEE Computer Society Annual Symposium on VLSI ◽

10.1109/isvlsi.2004.1339501 ◽

2004 ◽

Cited By ~ 15

Author(s):

M.T. Niemier ◽

P.M. Kogge

Keyword(s):

Building Block ◽

Nano Scale

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Suppression of jitter effects in A/D converters through sigma-delta sampling

IEEE Computer Society Annual Symposium on VLSI ◽

10.1109/isvlsi.2004.1339518 ◽

2004 ◽

Cited By ~ 3

Author(s):

A. Strak ◽

H. Tenhunen

Keyword(s):

Sigma Delta

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A configurable pipelined state machine as a hybrid ASIC and configurable architecture

IEEE Computer Society Annual Symposium on VLSI ◽

10.1109/isvlsi.2004.1339551 ◽

2004 ◽

Cited By ~ 1

Author(s):

P. Zipf ◽

C. Stotzler ◽

M. Glesner

Keyword(s):

State Machine ◽

Configurable Architecture

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An efficient test vector ordering method for low power testing

IEEE Computer Society Annual Symposium on VLSI ◽

10.1109/isvlsi.2004.1339559 ◽

2004 ◽

Cited By ~ 5

Author(s):

X. Kavousianos ◽

D. Bakalis ◽

M. Bellos ◽

D. Nikolos

Keyword(s):

Low Power ◽

Test Vector ◽

Low Power Testing ◽

Efficient Test ◽

Power Testing

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Behavioural scheduling to balance the bit-level computational effort

IEEE Computer Society Annual Symposium on VLSI ◽

10.1109/isvlsi.2004.1339515 ◽

2004 ◽

Author(s):

M.C. Molina ◽

R. Ruiz-Sautua ◽

J.M. Mendias ◽

R. Hermida

Keyword(s):

Computational Effort

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FPGA placement and routing using particle swarm optimization

IEEE Computer Society Annual Symposium on VLSI ◽

10.1109/isvlsi.2004.1339567 ◽

2004 ◽

Cited By ~ 22

Author(s):

V.G. Gudise ◽

G.K. Venayagamoorthy

Keyword(s):

Particle Swarm Optimization ◽

Particle Swarm ◽

Swarm Optimization ◽

Fpga Placement ◽

Placement And Routing

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Parallel programmable finite field GF (2/sup m/) multipliers

IEEE Computer Society Annual Symposium on VLSI ◽

10.1109/isvlsi.2004.1339564 ◽

2004 ◽

Cited By ~ 5

Author(s):

N. Iliev ◽

J.E. Stine ◽

N. Jachimiec

Keyword(s):

Finite Field

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Logical effort based design exploration of 64-bit adders using a mixed dynamic-CMOS/threshold-logic approach

IEEE Computer Society Annual Symposium on VLSI ◽

10.1109/isvlsi.2004.1339519 ◽

2004 ◽

Cited By ~ 4

Author(s):

P. Celinski ◽

S. Al-Sarawi ◽

D. Abbott ◽

S. Cotofana ◽

S. Vassiliadis

Keyword(s):

Threshold Logic ◽

Design Exploration ◽

Logic Approach

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Fault tolerant algorithms for network-on-chip interconnect

IEEE Computer Society Annual Symposium on VLSI ◽

10.1109/isvlsi.2004.1339507 ◽

2004 ◽

Cited By ~ 102

Author(s):

M. Pirretti ◽

G.M. Link ◽

R.R. Brooks ◽

N. Vijaykrishnan ◽

M. Kandemir ◽

...

Keyword(s):

Fault Tolerant ◽

Network On Chip ◽

On Chip

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Scan cell ordering for low power BIST

IEEE Computer Society Annual Symposium on VLSI ◽

10.1109/isvlsi.2004.1339558 ◽

2004 ◽

Cited By ~ 7

Author(s):

M. Bellos ◽

D. Bakalis ◽

D. Nikolos

Keyword(s):

Low Power

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