Threshold Logic Technology based E-cube Routing on a 4-dimensional hypercube

Hypercube network connection is formed by connecting different N number of nodes that are expressed as a power of 2. If each node has an address of m bits then the total number of nodes in the Hypercube network is N=2^m. In calculating the predefined routing path for the case of this E-cube network, we apply deterministic algorithm which gives a deadlock free concept. For determining predefined routing path, node addresses involved in the path are calculated by using the exclusive operation, firstly, on the node addresses of source and destination, next, on the derived nodes according to the algorithm. In the present work, the Exclusive-OR operation is performed with the help of electron-tunneling based XOR gate which is made up of Multiple input threshold logic gate. This multiple input threshold logic gate technology is really different from the existing one. By using an emerging technology we are capable of making an electronic circuit with high speed, low cost, high concentration density, light in weight, reduced gate numbers and low power consumption. This technology is relies on the condition of linear threshold logic and electron-tunneling event. When we are interested in implementing a circuit, a multi-inputs but one-output based logic-gate will be taken account of consideration. In this work, we have designed an E-cube Routing on a 4-dimensional hypercube to find out the node addresses for predefining the deadlock free routing path from source to destination. To develop this “E-cube Routing on a 4-dimensional hypercube”, we must require a specific logic called Exclusive-OR gate and for this, some small components like 2-input OR gate, 2-input AND gates of different input conditions are essential. After arranging this XOR gate in a pattern discussed in section 2, a desired circuit is implemented. All the circuit we are intended to construct are given in due places with their threshold logic and simulation set, the simulation results are provided as well. Different truth tables, derivation of threshold logic expressions are given for clear understanding. We have taken our consideration of whether the present work circuits are faster or slower than the circuits of CMOS based- and Single electron transistor (SET) based-circuits. The power consumed at the time of tunneling event for a circuit is measured and sensed that it exists in the range between 10meV to 250meV which is very small amount. All the combinational circuits we have presented in this work are of ‘generic multiple input threshold logic gate’-based.

An Accumulator using Electron Tunneling Through Tunnel Junction

Instead of an existing logical Technology, by using an emerging technology we will be able to make an electronic circuit with high speed, low cost, high concentration density, light in weight, reduced gate numbers and low power consumption. This technology is based on the linear threshold logic condition and electron-tunneling event. At the time of implementing a circuit, a multi-inputs but one-output based logic-node will be brought in our consideration. In this work, we have designed a 1-bit accumulator and then implemented it. To develop an accumulator, some small components like 2-input AND, 3-input AND, 3-input OR, 8-input OR, 9-input OR gate and above all a JK Flip-flop (for 1-bit) are to be collected and connected them in logical order to obtain the proper circuit. After verifying all their characteristics with the results obtained from the simulator, we have built a 1-bit accumulator. All the small components are provided in due places. They are analyzed, detected their threshold logic equations, shown their threshold logic gates (TLGs), tabulated their truth tables, drawn their input-output waveforms, given their respective circuits with exact parameter values. In the accumulator, there are nine control variables S1 through S9 in view of performing the operations (i) Addition, (ii) clear, (iii) complement, (iv) AND, (v) OR, (vi) XOR, (vii) Right-shift, (viii) Left-shift and (ix) increment with positive triggering clock pulses. Whether our present work’s circuits are faster or slower with respect to the similar circuits of CMOS based- and Single electron transistor (SET) based circuits are compared and observed that our TLG based circuits are faster than the CMOS and SET based circuits. The power consumed for tunneling event for a circuit is measured and sensed that it would remain in the range of 10meV to 250meV which is low. All the circuits we have presented in this work are of ‘generic multiple input threshold logic gate’ which is elaborately discussed.

A High-Speed Bidirectional Register with Parallel Loading using single electron Threshold Logic Technology

In this work we have concentrated our attention to a High Speed 4-bit Bidirectional Register with Parallel Loading counting on the principle of threshold logic gates (TLG). After determining the number of logic gates and other circuits needed to complete the desired circuit for our work, we implement some gates and circuits made up of tunnel junctions and capacitances. Some multi-inputs (greater than two) are designed or implemented with the assistance of modified version of the generic multi-input TLG. The types of gates suitable for the implementing the bidirectional Register are 3-input AND, 3-input NAND and 4-input OR gates, in addition an inverter and a more complex circuits like 4:1 Multiplexer are the part and parcel of the desired device. With the help of a 3-input AND gate and a 4-input OR gate, a 4:1 Multiplexer is built. By using the 3-input NAND gate a memory element – D Flip-flop is constructed. At last 4 number of 4:1 Multiplexers and another four number of D Flip-flops are combined in a parallel pattern to implement a 4-bit Bidirectional Register with Parallel Loading. Each component is made after analyzing their corresponding threshold linear equations. After constructing the threshold circuits, again they are formed by using the parameters as capacitors, tunnel junctions with their internal resistances. All the circuit, which are constructed, are verified by simulation with the help of SIMON and the result obtained are investigated and found that they are matched with the theoretical results. For comparing the fastness of our circuit with the CMOS-based or single electron transistor (SET) based circuit, the processing delays of all gates/ circuits are determined. How much power they consume are measured as well. Comparing the delays of CMOS-based and SET based circuit with the TLG based circuit we have decided that our 4-bit Bidirectional Register with Parallel Loading is speedier.

Tunable Sub Threshold Logic Design Through Adaptive Feedback Equalization

An Efficient tunable subthreshold logic circuit planned by utilizing adaptive feedback equalization circuit. This circuit utilized in the Ladner Fischer adder. This circuit utilized in a successive advanced logic circuit to moderate the cycle variety impacts and lessen the prevailing spillage energy part in the subthreshold area. Feedback equalizer circuit changes the switching edge of its inverter. It depends on the output of the flip-flop in the past cycle to lessen the charging and releasing season of the flip-flop's information capacitance. Besides, the more modest info capacitance of the feedback equalizer lessens the switching season of the last door in the combinational logic block. Likewise present point by point energy-performance models of the adaptive feedback equalizer circuit.

Logic Synthesis for Emerging Technologies

Emerging technologies are being considered to replace the conventional CMOS-based design that seems arriving to its end of life due to the limits of MOS transistor shrinking. However, since those novel devices are not necessarily switch-based ones, the traditional AND/OR logic synthesis process in the digital integrated circuit design flow tends to become inefficient, whereas threshold logic paradigm seems to be more appropriate for them. In this context, different methods for threshold logic synthesis, suitable for emerging technologies, are reviewed in this paper. The majority logic based design is also discussed herein since it represents a subset of threshold logic domain, and many new technologies have presented the 3-input majority Boolean function as the most basic logic gate. Experimental data, presented in previous works, are used to illustrate and compare the performance of the state-ofthe-art logic synthesis methods related to