A 32 Gb/s CMOS Receiver with Analog Carrier Recovery and Synchronous QPSK Demodulation

2021 ◽  
pp. 1-1
Author(s):  
Sangyeop Lee ◽  
Shuhei Amakawa ◽  
Takeshi Yoshida ◽  
Shisuke Hara ◽  
Minoru Fujishima
Keyword(s):  
Carrier Recovery ◽  
Cmos Receiver

A 6-mW-DC-Power 300-GHz CMOS Receiver for Near-Field Wireless Communications

2019 ◽  
Author(s):  
Sangyeop Lee ◽  
Ruibing Dong ◽  
Shinsuke Hara ◽  
Kyoya Takano ◽  
Shuhei Amakawa ◽  
...  
Keyword(s):  
Wireless Communications ◽  
Near Field ◽  
Dc Power ◽  
Cmos Receiver

scholarly journals Design of Short, High-Rate DVB-S2-Like Semi-Regular LDPC Codes

2008 ◽  
Vol 2008 ◽  
pp. 1-4
Author(s):  
Luca Barletta ◽  
Arnaldo Spalvieri
Keyword(s):  
Coded Modulation ◽  
High Rate ◽  
Parity Check ◽  
Code Length ◽  
Carrier Recovery ◽  
Low Density Parity Check ◽  
Novel Approach ◽  
Parity Check Codes ◽  
Moderate Length

This work focuses on high-rate () moderate-length () low-density parity-check codes. High-rate codes allow to maintain good quality of the preliminary decisions that are used in carrier recovery, while a moderate code length allows to keep the latency low. The interleaver of the LDPC matrix that we consider is inspired to the DVB-S2 standard one. A novel approach for avoiding short cycles is analyzed. A modified BP decoding algorithm is applied in order to deal with longer cycles. Simulations and results for the AWGN channel are presented, both for BPSK signalling and for coded modulation based on the partition .

Clock-aided carrier recovery in trellis-coded PSK

1989 ◽  
Vol 7 (9) ◽  
pp. 1307-1317 ◽  
Author(s):  
F. Lorenzelli ◽  
L. Testa ◽  
M. Visintin ◽  
E. Biglieri ◽  
M. Pent
Keyword(s):  
Carrier Recovery ◽  
Trellis Coded

Divide-by-8 phase detector MMIC for PLL-based carrier recovery in E-band communication

2015 ◽  
Author(s):  
T. Messinger ◽  
D. Muller ◽  
J. Antes ◽  
S. Wagner ◽  
A. Tessmann ◽  
...  
Keyword(s):  
Phase Detector ◽  
Carrier Recovery
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