Low power mixed analog-digital signal processing

2000 ◽  
Author(s):  
M. Duppils ◽  
C. Svensson
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Low Power ◽  
Digital Signal

Low-Power Digital Signal Processing Using Approximate Adders

2013 ◽  
Vol 32 (1) ◽  
pp. 124-137 ◽  
Author(s):  
Vaibhav Gupta ◽  
Debabrata Mohapatra ◽  
Anand Raghunathan ◽  
Kaushik Roy
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Low Power ◽  
Digital Signal

scholarly journals Baseband I/Q regeneration Method for Direct Conversion Receiver to nullify effect of I/Q mismatch

2016 ◽  
Vol 5 (3) ◽  
pp. 50 ◽  
Author(s):  
M. Shah ◽  
S. Gupta
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Low Power ◽  
Digital Signal ◽  
Direct Conversion ◽  
Performance Degradation ◽  
Wireless Receiver ◽  
Novel Method ◽  
The One

Direct Conversion Receiver is the choice of the today’s designer for low power compact wireless receiver. DCR is attractive due to low power, small size and highly monolithic integratable structure, but distortions affect its performance.  I/Q mismatch is the one of the major distortion which is responsible for performance degradation.  In this paper, a novel method for Direct Conversion Receiver is suggested, which makes it insensitive to the I/Q mismatch. Here the classical homodyne architecture is modified to nullify effect of I/Q mismatch. The proposed method can be implemented in the Digital Signal Processing (DSP) back-end section also.  This feature makes it acceptable in the already designed/functioning classical homodyne architecture based receiver.

scholarly journals Design of Low-Power High-Speed Truncation-Error-Tolerant Adder and Its Application in Digital Signal Processing

2010 ◽  
Vol 18 (8) ◽  
pp. 1225-1229 ◽  
Author(s):  
Ning Zhu ◽  
Wang Ling Goh ◽  
Weija Zhang ◽  
Kiat Seng Yeo ◽  
Zhi Hui Kong
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Low Power ◽  
High Speed ◽  
Truncation Error ◽  
Digital Signal

A low-power SHA-3 designs using embedded digital signal processing slice on FPGA

2016 ◽  
Vol 55 ◽  
pp. 138-152 ◽  
Author(s):  
Dur-e-Shahwar Kundi ◽  
Arshad Aziz
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Low Power ◽  
Digital Signal

scholarly journals Efficient High Speed Computing Low Power Multiplier Architecture using Vedic Mathematics For Digital Signal Processing Applications

2020 ◽  
Vol V9 (05) ◽  
Author(s):  
Dr. S. Sridhar ◽  
Monisha Tanniru ◽  
Rasagna Sidhantam ◽  
Sai Viswanath Singamsetty ◽  
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Low Power ◽  
High Speed ◽  
Digital Signal ◽  
Vedic Mathematics ◽  
Low Power Multiplier
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