ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514)

2002 ◽

Author(s):

C.J. Debono ◽

F. Maloberti ◽

J. Micallef

Keyword(s):

Low Voltage ◽

Rf Applications

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Speeding up power estimation of embedded software

ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514) ◽

10.1109/lpe.2000.876780 ◽

2002 ◽

Cited By ~ 1

Author(s):

A. Sama ◽

M. Balakrishnan ◽

J.F.M. Theeuwen

Keyword(s):

Power Estimation ◽

Embedded Software

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Analysis and design of low-phase-noise ring oscillators

ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514) ◽

10.1109/lpe.2000.876805 ◽

2002 ◽

Author(s):

L. Dai ◽

R. Harjani

Keyword(s):

Phase Noise ◽

Ring Oscillators ◽

Analysis And Design ◽

Low Phase Noise

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An asynchronous matrix-vector multiplier for discrete cosine transform

ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514) ◽

10.1109/lpe.2000.876799 ◽

2002 ◽

Author(s):

Kyeounsoo Kim ◽

P.A. Beerel ◽

Youpyo Hong

Keyword(s):

Discrete Cosine Transform ◽

Cosine Transform ◽

Matrix Vector

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A low power unified cache architecture providing power and performance flexibility

ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514) ◽

10.1109/lpe.2000.876794 ◽

2002 ◽

Author(s):

A. Malik ◽

B. Moyer ◽

D. Cermak

Keyword(s):

Low Power ◽

Cache Architecture ◽

And Performance

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Voltage dependent gate capacitance and its impact in estimating power and delay of CMOS digital circuits with low supply voltage

ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514) ◽

10.1109/lpe.2000.876790 ◽

2002 ◽

Author(s):

K. Nose ◽

Soo-Ik Chae ◽

T. Sakurai

Keyword(s):

Digital Circuits ◽

Supply Voltage ◽

Gate Capacitance ◽

Voltage Dependent ◽

Low Supply Voltage

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Low power self-timed radix-2 division

ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514) ◽

10.1109/lpe.2000.876784 ◽

2002 ◽

Author(s):

Jae-Hee Won ◽

Kiyoung Choi

Keyword(s):

Low Power

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"Cool low power" 1 GHz multi-port register file and dynamic latch in 1.8 V, 0.25 μm SOI and bulk technology

ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514) ◽

10.1109/lpe.2000.876782 ◽

2002 ◽

Author(s):

R.V. Joshi ◽

W. Hwang ◽

S.C. Wilson ◽

C.T. Chuang

Keyword(s):

Low Power ◽

Register File ◽

Bulk Technology

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Model and analysis for combined package and on-chip power grid simulation

ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514) ◽

10.1109/lpe.2000.876778 ◽

2002 ◽

Author(s):

R. Panda ◽

D. Blaauw ◽

R. Chaudhry ◽

V. Zolotov ◽

B. Young ◽

...

Keyword(s):

Power Grid ◽

Grid Simulation ◽

On Chip

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Voltage scheduling in the IpARM microprocessor system

ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514) ◽

10.1109/lpe.2000.876764 ◽

2002 ◽

Author(s):

T. Pering ◽

T. Burd ◽

R. Brodersen

Keyword(s):

Microprocessor System

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ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514)
Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By ACM

A low-voltage CMOS multiplier for RF applications

Speeding up power estimation of embedded software

Analysis and design of low-phase-noise ring oscillators

An asynchronous matrix-vector multiplier for discrete cosine transform

A low power unified cache architecture providing power and performance flexibility

Voltage dependent gate capacitance and its impact in estimating power and delay of CMOS digital circuits with low supply voltage

Low power self-timed radix-2 division

"Cool low power" 1 GHz multi-port register file and dynamic latch in 1.8 V, 0.25 μm SOI and bulk technology

Model and analysis for combined package and on-chip power grid simulation

Voltage scheduling in the IpARM microprocessor system

Export Citation Format

ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By ACM

A low-voltage CMOS multiplier for RF applications

Speeding up power estimation of embedded software

Analysis and design of low-phase-noise ring oscillators

An asynchronous matrix-vector multiplier for discrete cosine transform

A low power unified cache architecture providing power and performance flexibility

Voltage dependent gate capacitance and its impact in estimating power and delay of CMOS digital circuits with low supply voltage

Low power self-timed radix-2 division

"Cool low power" 1 GHz multi-port register file and dynamic latch in 1.8 V, 0.25 μm SOI and bulk technology

Model and analysis for combined package and on-chip power grid simulation

Voltage scheduling in the IpARM microprocessor system

ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514)
Latest Publications