Logic Design and Power Optimization of Floating-Point Multipliers

Under IEEE-754 standard, for the current situation of excessive time and power consumption of multiplication operations in single-precision floating-point operations, the expanded boothwallace algorithm is used, and the partial product caused by booth coding is rounded and predicted with the symbolic expansion idea, and the partial product caused by single-precision floating-point multiplication and the accumulation of partial products are optimized, and the flowing water is used to improve the throughput. Based on this, a series of verification and synthesis simulations are performed using the SMIC-7 nm standard cell process. It is verified that the new single-precision floating-point multiplier can achieve a smaller power share compared to the conventional single-precision floating-point multiplier.

Assertion Driven Modified Booth Encoding and Post Computation Model for Speed MAC Applications

The Multiply-Accumulate Unit (MAC) is the core computational block in many DSP and wireless application but comes with more complicated architectures. Moreover the MAC block also decides the energy consumption and the performance of the overall design; due to its lies in the maximal path delay critical propagation. Developing high performance and energy optimized MAC core is essential to optimized DSP core. In this work, a high speed and low power signed booth radix enabled MAC Unit is proposed with highly configurable assertion driven modified booth algorithm (AD-MBE). The proposed booth core is based on core optimized booth radix-4 with hierarchical partial product accumulation design and associated path delay optimization and computational complexity reduction. Here all booth generated partial products are added as post summation adder network which consists of carry select adder (CSA) & carry look ahead (CLA) sequentially which narrow down the energy and computational complexity. Here increasing the operating frequency is achieved by accumulating encoding bits of each of the input operand into assertion unit before generating end results instead of going through the entire partial product accumulation. The FPGA implementation of the proposed signed asserted booth radix-4 based MAC shows significant complexity reduction with improved system performance as compared to the conventional booth unit and conventional array multiplier.

Compressor based approximate multiplier architectures for media processing applications

Approximate computing is an attractive technique to gain substantial improvement in the area, speed, and power in applications where exact computation is not required. This paper proposes two improved multiplier designs based on a new 4:2 approximate compressor circuit to simplify the hardware at the partial product reduction stage. The proposed multiplier designs are targeted towards error-tolerant applications. Exhaustive error and hardware analysis has been carried out on the existing and proposed multiplier designs. The results prove that the proposed approximate multiplier architecture performs better than the existing architectures without significant compromise on quality metrics. Experimental results show that die-area and power consumed are reduced upto 28%, and 25.29% respectively in comparison with the existing designs without significant compromise on accuracy.

Analysis of Existing and Proposed 3-Bit and Multi-Bit Multiplier Algorithms for FIR Filters and Adaptive Channel Equalizers on FPGA

Different multiplication algorithms have different performance characteristics. Some are good at speed while others consume less area when implemented on hardware, like Field Programmable Gate Array (FPGA)-the advanced implementation technology for DSP systems. The eminent parallel and sequential multiplication algorithms include Shift and Add, Wallace Tree, Booth, and Array. The multiplier optimization attempts have also been reported in adders used for partial product addition. In this paper, analogous to conventional multipliers, two new multiplication algorithms implemented on FPGA are shown and compared with conventional algorithms as stand-alone and by using them in the implementation of FIR filters and adaptive channel equalizer using the LMS algorithm. The work is carried out on Spartan-6 FPG that may be extended for any type of FPGA. Results are compared in terms of resource utilization, power consumption, and maximum achieved frequency. The results show that for a small length of coefficients like 3-bit, the proposed algorithms work very well in terms of achieved frequency, consumed power, and even resource utilization. Whilst for the length greater than 3-bit, the Pipelined multiplier is much better in frequency than the proposed and conventional ones, and the Booth multiplier consumes fewer resources in terms of lookup tables.

A Hybrid Radix-4 and Approximate Logarithmic Multiplier for Energy Efficient Image Processing

Multiplication is an essential image processing operation commonly implemented in hardware DSP cores. To improve DSP cores’ area, speed, or energy efficiency, we can approximate multiplication. We present an approximate multiplier that generates two partial products using hybrid radix-4 and logarithmic encoding of the input operands. It uses the exact radix-4 encoding to generate the partial product from the three most significant bits and the logarithmic approximation with mantissa trimming to approximate the partial product from the remaining least-significant bits. The proposed multiplier fills the gap between highly accurate approximate non-logarithmic multipliers with a complex design and less accurate approximate logarithmic multipliers with a more straightforward design. We evaluated the multiplier’s efficiency in terms of error, energy (power-delay-product) and area utilisation using NanGate 45 nm. The experimental results show that the proposed multiplier exhibits good area utilisation and energy consumption and behaves well in image processing applications.

E-Marketing, Keragaman Produk dan Keputusan Pembelian (Studi Pada UKM Batik Surya 26 Kabupaten Tuban)

The purpose of this study is to influence, e-marketing and product diversity in UKM Batik Surya 26 Tuban Regency, either partially or simultaneously on purchasing decisions. This research was conducted using quantitative descriptive methods. The sampling technique used was non-probability sampling with the incidental sampling method used as a sampling method, in order to obtain a sample of 97 people and hypothesis testing using multiple linear regression analysis. The conclusion of the results of this study is that e-marketing partially has a significant effect on purchasing decisions, partial product diversity has a significant effect on purchasing decisions, and e-marketing and product diversity simultaneously has a significant effect on purchasing decisions.