A Reduced High-Level-Language Instruction Set

IEEE Micro ◽  
1984 ◽  
Vol 4 (3) ◽  
pp. 55-67 ◽  
Author(s):  
Peter Schulthess
2015 ◽  
Vol 76 (12) ◽  
Author(s):  
K. Umapathy ◽  
V. Balaji ◽  
V. Duraisamy ◽  
S. S. Saravanakumar

In this paper presents the implementation of wavelet based medical image fusion on FPGA is performed using high level language C. The high- level instruction set of the image processor is based on the operation of image algebra like convolution, additive max-min, and multiplicative max-min. The above parameters are used to increase the speed. The FPGA based microprocessor is used to accelerate the extraction of texture features and high level C programming language is used for hardware design. This proposed hardware architecture reduces the hardware utilizations and best suitable for low power applications. The paper describes the programming interface of the user and outlines the approach for generating FPGA architectures dynamically for the image co-processor. It also presents sample implementation results (speed, area) for different neighborhood operations.


2012 ◽  
Vol 47 (6) ◽  
pp. 1-12 ◽  
Author(s):  
Christophe Dubach ◽  
Perry Cheng ◽  
Rodric Rabbah ◽  
David F. Bacon ◽  
Stephen J. Fink

1978 ◽  
Vol 6 (8) ◽  
pp. 20-22
Author(s):  
Lyle A. Cox ◽  
James R. McGraw ◽  
Charles S. Wetherell

Aphasiology ◽  
1997 ◽  
Vol 11 (1) ◽  
pp. 39-57 ◽  
Author(s):  
Jennifer B. Lethlean ◽  
Bruce E. Murdoch

Author(s):  
Irfan Uddin

The microthreaded many-core architecture is comprised of multiple clusters of fine-grained multi-threaded cores. The management of concurrency is supported in the instruction set architecture of the cores and the computational work in application is asynchronously delegated to different clusters of cores, where the cluster is allocated dynamically. Computer architects are always interested in analyzing the complex interaction amongst the dynamically allocated resources. Generally a detailed simulation with a cycle-accurate simulation of the execution time is used. However, the cycle-accurate simulator for the microthreaded architecture executes at the rate of 100,000 instructions per second, divided over the number of simulated cores. This means that the evaluation of a complex application executing on a contemporary multi-core machine can be very slow. To perform efficient design space exploration we present a co-simulation environment, where the detailed execution of instructions in the pipeline of microthreaded cores and the interactions amongst the hardware components are abstracted. We present the evaluation of the high-level simulation framework against the cycle-accurate simulation framework. The results show that the high-level simulator is faster and less complicated than the cycle-accurate simulator but with the cost of losing accuracy.


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