Deadlock-free generic routing algorithms for 3-dimensional Networks-on-Chip with reduced vertical link density topologies

2013 ◽  
Vol 59 (7) ◽  
pp. 528-542 ◽  
Author(s):  
Haoyuan Ying ◽  
Ashok Jaiswal ◽  
Thomas Hollstein ◽  
Klaus Hofmann
VLSI Design ◽  
2009 ◽  
Vol 2009 ◽  
pp. 1-15 ◽  
Author(s):  
Faizal A. Samman ◽  
Thomas Hollstein ◽  
Manfred Glesner

This paper presents a network-on-chip (NoC) with flexible infrastructure based on dynamic wormhole packet identity management. The NoCs are developed based on a VHDL approach and support the design flexibility. The on-chip router uses a wormhole packet switching method with a synchronous parallel pipeline technique. Routing algorithms and dynamic wormhole local packet identity (ID-tag) mapping management are proposed to support a wire sharing methodology and an ID slot division multiplexing technique. At each communication link, flits belonging to the same message have the same local ID-tag, and the ID-tag is updated before the packet enters the next communication link by using an ID-tag mapping management unit. Therefore, flits from different messages can be interleaved, identified, and routed according to their allocated ID slots. Our NoC guarantees in order and lossless message delivery.


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