A compiler framework for recovery code generation in general speculative optimizations

2004 ◽  
Author(s):  
Jin Lin ◽  
Wei-Chung Hsu ◽  
Pen-Chung Yew ◽  
Roy Dz-Ching Ju ◽  
Tin-Fook Ngai
Keyword(s):  
Code Generation ◽  
Compiler Framework ◽  
Recovery Code ◽  
Speculative Optimizations

scholarly journals Recovery code generation for general speculative optimizations

2006 ◽  
Vol 3 (1) ◽  
pp. 67-89 ◽  
Author(s):  
Jin Lin ◽  
Wei-Chung Hsu ◽  
Pen-Chung Yew ◽  
Roy Dz-Ching Ju ◽  
Tin-Fook Ngai
Keyword(s):  
Code Generation ◽  
Recovery Code ◽  
Speculative Optimizations

scholarly journals A compiler framework for the reduction of worst-case execution times

2010 ◽  
Vol 46 (2) ◽  
pp. 251-300 ◽  
Author(s):  
Heiko Falk ◽  
Paul Lokuciejewski
Keyword(s):  
Real Time ◽  
Code Generation ◽  
Optimization Techniques ◽  
Design Flow ◽  
Tool Support ◽  
Worst Case ◽  
Real Time System ◽  
Worst Case Execution Time ◽  
Compiler Framework ◽  
Time Systems

Abstract The current practice to design software for real-time systems is tedious. There is almost no tool support that assists the designer in automatically deriving safe bounds of the worst-case execution time (WCET) of a system during code generation and in systematically optimizing code to reduce WCET. This article presents concepts and infrastructures for WCET-aware code generation and optimization techniques for WCET reduction. All together, they help to obtain code explicitly optimized for its worst-case timing, to automate large parts of the real-time software design flow, and to reduce costs of a real-time system by allowing to use tailored hardware.

scholarly journals A compiler framework for speculative optimizations

2004 ◽  
Vol 1 (3) ◽  
pp. 247-271 ◽  
Author(s):  
Jin Lin ◽  
Tong Chen ◽  
Wei-Chung Hsu ◽  
Pen-Chung Yew ◽  
Roy Dz-Ching Ju ◽  
...  
Keyword(s):  
Compiler Framework ◽  
Speculative Optimizations

ECC-Based Bit-Write Reduction Code Generation for Non-Volatile Memory

2015 ◽  
Vol E98.A (12) ◽  
pp. 2494-2504 ◽  
Author(s):  
Masashi TAWADA ◽  
Shinji KIMURA ◽  
Masao YANAGISAWA ◽  
Nozomu TOGAWA
Keyword(s):  
Code Generation ◽  
Non Volatile Memory ◽  
Volatile Memory

Privacy Concern Code Generation Using Crypto Neural Scheme

2019 ◽  
Vol 7 (5) ◽  
pp. 824-828
Author(s):  
Anaswara Venunadh ◽  
Shruthi N ◽  
Mannar Mannan
Keyword(s):  
Code Generation ◽  
Privacy Concern

Realization of NAND FLASH Control Glueless Interface Circuit

2014 ◽  
Vol 1008-1009 ◽  
pp. 659-662
Author(s):  
Hai Ke Liu ◽  
Shun Wang ◽  
Xin Gna Kang ◽  
Jin Liang Wang
Keyword(s):  
Error Correction ◽  
Code Generation ◽  
Nand Flash ◽  
Timing Control ◽  
Interface Circuit ◽  
Advantages And Disadvantages ◽  
Operation Sequence ◽  
Control Interface

The article realization of NAND FLASH control glueless interface circuit based on FPGA,comparing the advantages and disadvantages of the NAND Flash and analysising the function of control interface circuit. The control interface circuit can correct carry out the SRAM timing-input block erase, page reads, page programming, state read instructions into the required operation sequence of NAND Flash, greatly simplifies the NAND FLASH read and write timing control. According to the ECC algorithm,the realization method of ECC check code generation,error search,error correction is described.The function of operate instructions of the NAND Flash control interface circuit designed in this paper is verified on Xillinx Spartan-3 board, and the frequency can reach 100MHz.

An experiment in table driven code generation

1982 ◽  
Vol 17 (6) ◽  
pp. 32-43 ◽  
Author(s):  
Susan L. Graham ◽  
Robert R. Henry ◽  
Robert A. Schulman
Keyword(s):  
Code Generation
Sign in / Sign up

Export Citation Format

Share Document