scholarly journals A compiler framework for the reduction of worst-case execution times

2010 ◽  
Vol 46 (2) ◽  
pp. 251-300 ◽  
Author(s):  
Heiko Falk ◽  
Paul Lokuciejewski
Keyword(s):  
Real Time ◽  
Code Generation ◽  
Optimization Techniques ◽  
Design Flow ◽  
Tool Support ◽  
Worst Case ◽  
Real Time System ◽  
Worst Case Execution Time ◽  
Compiler Framework ◽  
Time Systems

Abstract The current practice to design software for real-time systems is tedious. There is almost no tool support that assists the designer in automatically deriving safe bounds of the worst-case execution time (WCET) of a system during code generation and in systematically optimizing code to reduce WCET. This article presents concepts and infrastructures for WCET-aware code generation and optimization techniques for WCET reduction. All together, they help to obtain code explicitly optimized for its worst-case timing, to automate large parts of the real-time software design flow, and to reduce costs of a real-time system by allowing to use tailored hardware.

Use of Measurements in Worst-Case Execution Time Estimation for Real-Time Systems

2021 ◽  
Author(s):  
Jessica Junia Santillo Costa ◽  
Romulo Silva de Oliveira ◽  
Luis Fernando Arcaro
Keyword(s):  
Real Time ◽  
Execution Time ◽  
Time Estimation ◽  
Real Time Systems ◽  
Worst Case ◽  
Worst Case Execution Time ◽  
Time Systems

scholarly journals Worst-case execution-time analysis for embedded real-time systems

2003 ◽  
Vol 4 (4) ◽  
pp. 437-455 ◽  
Author(s):  
Jakob Engblom ◽  
Andreas Ermedahl ◽  
Mikael Sjödin ◽  
Jan Gustafsson ◽  
Hans Hansson
Keyword(s):  
Real Time ◽  
Execution Time ◽  
Real Time Systems ◽  
Time Analysis ◽  
Worst Case ◽  
Worst Case Execution Time ◽  
Time Systems

Novel prioritized LRU circuits for shared cache in computer systems

2020 ◽  
Vol 34 (23) ◽  
pp. 2050242
Author(s):  
Yao Wang ◽  
Lijun Sun ◽  
Haibo Wang ◽  
Lavanya Gopalakrishnan ◽  
Ronald Eaton
Keyword(s):  
Real Time ◽  
High Performance ◽  
Cmos Technology ◽  
Cache Replacement ◽  
Worst Case ◽  
Shared Cache ◽  
Cache Access ◽  
Worst Case Execution Time ◽  
Real Time Applications ◽  
Time Systems

Cache sharing technique is critical in multi-core and multi-threading systems. It potentially delays the execution of real-time applications and makes the prediction of the worst-case execution time (WCET) of real-time applications more challenging. Prioritized cache has been demonstrated as a promising approach to address this challenge. Instead of the conventional prioritized cache schemes realized at the architecture level by using cache controllers, this work presents two prioritized least recently used (LRU) cache replacement circuits that directly accomplish the prioritization inside the cache circuits, hence significantly reduces the cache access latency. The performance, hardware and power overheads due to the proposed prioritized LRU circuits are investigated based on a 65 nm CMOS technology. It shows that the proposed circuits have very low overhead compared to conventional cache circuits. The presented techniques will lead to more effective prioritized shared cache implementations and benefit the development of high-performance real-time systems.

Reconfiguration of Uniprocessor Sporadic Real-Time Systems

2011 ◽  
pp. 167-189 ◽  
Author(s):  
Laurent George ◽  
Pierre Courbin
Keyword(s):  
Sensitivity Analysis ◽  
Real Time ◽  
Performance Tuning ◽  
Real Time Systems ◽  
Software Faults ◽  
Worst Case ◽  
Task Model ◽  
Worst Case Execution Time ◽  
On Line ◽  
Time Systems

In this chapter the authors focus on the problem of reconfiguring embedded real-time systems. Such reconfiguration can be decided either off-line to determine if a given application can be run on a different platform, while preserving the timeliness constraints imposed by the application, or on-line, where a reconfiguration should be done to adapt the system to the context of execution or to handle hardware or software faults. The task model considered in this chapter is the classical sporadic task model defined by a Worst Case Execution Time (WCET), a minimum inter-arrival time (also denoted the minimum Period) and a late termination deadline. The authors consider two preemptive scheduling strategies: Fixed Priority highest priority first (FP) and Earliest Deadline First (EDF). They propose a sensitivity analysis to handle reconfiguration issues. Sensitivity analysis aims at determining acceptable deviations from the specifications of a problem due to evolutions in system characteristics (reconfiguration or performance tuning). They present a state of the art for sensitivity analysis in the case of WCETs, Periods and Deadlines reconfigurations and study to what extent sensitivity analysis can be used to decide on the possibility of reconfiguring a system.

A WCET Test Method Based on Associative Process Communication

2014 ◽  
Vol 577 ◽  
pp. 865-872
Author(s):  
Jun Yi Li ◽  
Yi Zhang ◽  
Ren Fa Li
Keyword(s):  
Real Time ◽  
Test Method ◽  
Basic Block ◽  
Worst Case ◽  
Real Time System ◽  
The Real ◽  
Process Communication ◽  
Associative Process ◽  
Worst Case Execution Time ◽  
Time Requirements

The Real-time system estimates the worst-case execution time (WCET) of the program to ensure the real-time requirements of the system. In this paper, a test method based on Associative Process Communication (APC) is put forward. First it tests the WCET value of basic blocks of ICFG through the use of APC algorithm, and then estimates the WCET by analyzing the worst execution path of the basic block. APC test method tests all benchmarks of Mälardalen. And the test results show that the proposed test method is precise and effective, and the test error is within the theoretical analysis.

An Overview of Worst-Case Execution Time Estimation for Embedded Programs

2014 ◽  
Vol 651-653 ◽  
pp. 624-629
Author(s):  
Liang Liang Kong ◽  
Lin Xiang Shi ◽  
Lin Chen
Keyword(s):  
Embedded Systems ◽  
Real Time ◽  
Execution Time ◽  
Time Estimation ◽  
Worst Case ◽  
Performance Metric ◽  
Worst Case Execution Time ◽  
Hard Real Time ◽  
Time Systems

Most embedded systems are real-time systems, so real-time is an important performance metric for embedded systems. The worst-case execution time (WCET) estimation for embedded programs could satisfy the requirement of hard real-time evaluation, so it is widely used in embedded systems evaluation. Based on sufficient survey on the progress of WCET estimation around the world, it proposes a new classification of WCET estimation. After introducing the principle of WCET estimation, it mainly demonstrates various types of technologies to estimate WCET and classifies them into two main streams, namely, static and dynamic WCET estimations. Finally, it shows the development of WCET analysis tools.

Dynamic Partitioned Cache Memory for Real-Time MPSoCs with Mixed Criticality

2016 ◽  
Vol 25 (06) ◽  
pp. 1650062 ◽  
Author(s):  
Gang Chen ◽  
Kai Huang ◽  
Long Cheng ◽  
Biao Hu ◽  
Alois Knoll
Keyword(s):  
Real Time ◽  
Cache Memory ◽  
Time System ◽  
Worst Case ◽  
Real Time System ◽  
Average Performance ◽  
Shared Cache ◽  
Worst Case Execution Time ◽  
The One ◽  
Major Factors

Shared cache interference in multi-core architectures has been recognized as one of major factors that degrade predictability of a mixed-critical real-time system. Due to the unpredictable cache interference, the behavior of shared cache is hard to predict and analyze statically in multi-core architectures executing mixed-critical tasks, which will not only result in difficulty of estimating the worst-case execution time (WCET) but also introduce significant worst-case timing penalties for critical tasks. Therefore, cache management in mixed-critical multi-core systems has become a challenging task. In this paper, we present a dynamic partitioned cache memory for mixed-critical real-time multi-core systems. In this architecture, critical tasks can dynamically allocate and release the cache resourse during the execution interval according to the real-time workload. This dynamic partitioned cache can, on the one hand, provide the predicable cache performance for critical tasks. On the other hand, the released cache can be dynamically used by non-critical tasks to improve their average performance. We demonstrate and prototype our system design on the embedded FPGA platform. Measurements from the prototype clearly demonstrate the benefits of the dynamic partitioned cache for mixed-critical real-time multi-core systems.

Fault-Tolerant Task Scheduling for Mixed-Criticality Real-Time Systems

2016 ◽  
Vol 26 (01) ◽  
pp. 1750016 ◽  
Author(s):  
Junlong Zhou ◽  
Min Yin ◽  
Zhifang Li ◽  
Kun Cao ◽  
Jianming Yan ◽  
...  
Keyword(s):  
Real Time ◽  
Fault Tolerant ◽  
Transient Faults ◽  
Worst Case ◽  
Worst Case Execution Time ◽  
Time Systems ◽  
Certification Requirements ◽  
Different Levels ◽  
Mixed Criticality

Integration of safety-critical tasks with different certification requirements onto a common hardware platform has become a growing tendency in the design of real-time and embedded systems. In the past decade, great efforts have been made to develop techniques for handling uncertainties in task worst-case execution time, quality-of-service, and schedulability of mixed-criticality systems. However, few works take fault-tolerance as a design requirement. In this paper, we address the scheduling of fault-tolerant mixed-criticality systems to ensure the safety of tasks at different levels of criticalities in the presence of transient faults. We adopt task re-execution as the fault-tolerant technique. Extensive simulations were performed to validate the effectiveness of our algorithm. Simulation results show that our algorithm results in up to [Formula: see text] and [Formula: see text] improvement in system reliability and schedule feasibility as compared to existing techniques, which contributes to a more safe system.

scholarly journals PBench: A Parallel, Real-Time Benchmark Suite

2018 ◽  
Vol 1 (1) ◽  
pp. 178-186 ◽  
Author(s):  
Sevil Serttaş ◽  
Veysel Harun Şahin
Keyword(s):  
Real Time ◽  
Execution Time ◽  
Matrix Multiplication ◽  
Multiprocessor Systems ◽  
Time Analysis ◽  
Worst Case ◽  
Analysis Methods ◽  
Worst Case Execution Time ◽  
Benchmark Suite ◽  
Time Systems

Real-time systems are widely used from the automotive industry to the aerospace industry. The scientists, researchers, and engineers who develop real-time platforms, worst-case execution time analysis methods and tools need to compare their solutions to alternatives. For this purpose, they use benchmark applications. Today many of our computing systems are multicore and/or multiprocessor systems. Therefore, to be able to compare the effectiveness of real-time platforms, worst-case execution time analysis methods and tools, the research community need multi-threaded benchmark applications which scale on multicore and/or multiprocessor systems. In this paper, we present the first version of PBench, a parallel, real-time benchmark suite. PBench includes different types of multi-threaded applications which implement various algorithms from searching to sorting, matrix multiplication to probability distribution calculation. In addition, PBench provides single-threaded versions of all programs to allow side by side comparisons.

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