Dual Vdd and multi Vth cascaded inverters as level converter for clock distribution network

Level Converter

2019 Joint International Symposium on Electromagnetic Compatibility, Sapporo and Asia-Pacific International Symposium on Electromagnetic Compatibility (EMC Sapporo/APEMC) ◽

Jitter Estimation in a CMOS Tapered Buffer for an Application of Clock Distribution Network

10.23919/emctokyo.2019.8893857 ◽

2019 ◽

Author(s):

Muhammed Suhail Illikkal ◽

Jai Narayan Tripathi ◽

Hitesh Shrimali

Keyword(s):

Distribution Network ◽

Clock Distribution ◽

Power Efficient 3D Clock Distribution Network Design with TSV Count Optimization

Procedia Computer Science ◽

10.1016/j.procs.2016.07.197 ◽

2016 ◽

Vol 93 ◽

pp. 169-175 ◽

Cited By ~ 2

Author(s):

Nikhil Joshi ◽

John Reuben

Keyword(s):

Network Design ◽

Distribution Network ◽

Clock Distribution ◽

Power Efficient ◽

Distribution Network Design ◽

Low Power Resonant Rotary Global Clock Distribution Network Design

10.17918/etd-4573 ◽

2021 ◽

Author(s):

Ying Teng

Keyword(s):

Low Power ◽

Network Design ◽

Distribution Network ◽

Clock Distribution ◽

Distribution Network Design ◽

Global Clock ◽

Proceedings of the 2003 conference on Asia South Pacific design automation - ASPDAC ◽

Adaptive wire adjustment for bounded skew Clock Distribution Network

10.1145/1119772.1119820 ◽

2003 ◽

Author(s):

H. Saaied ◽

D. Al-Khalili ◽

A. Al-Khalili ◽

M. Nekili

Keyword(s):

Distribution Network ◽

Clock Distribution ◽

Globally Wireless Locally Wired (GloWiLoW): A Clock Distribution Network for Many-Core Systems

2018 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas.2018.8351041 ◽

2018 ◽

Cited By ~ 1

Author(s):

Qian Ding ◽

Benjamin J. Fletcher ◽

Terrence Mak

Keyword(s):

Distribution Network ◽

Clock Distribution ◽

Many Core

Chip-Package Hybrid Clock Distribution Network and DLL for Low Jitter Clock Delivery

IEEE Journal of Solid-State Circuits ◽

10.1109/jssc.2005.859882 ◽

2006 ◽

Vol 41 (1) ◽

pp. 274-286 ◽

Cited By ~ 6

Author(s):

D. Chung ◽

C. Ryu ◽

H. Kim ◽

C. Lee ◽

J. Kim ◽

...

Keyword(s):

Distribution Network ◽

Clock Distribution ◽

Low Jitter

A 3-D Low Jitter and Skew Clock Distribution Network Scheme Using LTCC Package Level Interposer With a Planar Cavity Resonator

IEEE Microwave and Wireless Components Letters ◽

10.1109/lmwc.2009.2024841 ◽

2009 ◽

Vol 19 (8) ◽

pp. 512-514

Author(s):

Woojin Lee ◽

Jaemin Kim ◽

Chunghyun Ryu ◽

Jongbae Park ◽

Jun Chul Kim ◽

...

Keyword(s):

Distribution Network ◽

Cavity Resonator ◽

Clock Distribution ◽

Low Jitter

A Low-Power Low-Skew Current-Mode Clock Distribution Network in 90nm CMOS Technology

2011 IEEE Computer Society Annual Symposium on VLSI ◽

10.1109/isvlsi.2011.80 ◽

2011 ◽

Cited By ~ 4

Author(s):

Naveen Kumar Kancharapu ◽

Marshnil Dave ◽

Veerraju Masimukkula ◽

Maryam Shojaei Baghini ◽

Dinesh Kumar Sharma

Keyword(s):

Low Power ◽

Distribution Network ◽

Current Mode ◽

Cmos Technology ◽

Clock Distribution ◽

Design of Low power & High Performance Multi Source H-Tree Clock Distribution Network

2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) ◽

10.1109/vlsidcs47293.2020.9179954 ◽

2020 ◽

Author(s):

V.G. Srivatsa ◽

Arunkumar P. Chavan ◽

Divakar Mourya

Keyword(s):

Low Power ◽

High Performance ◽

Distribution Network ◽

Clock Distribution ◽

2019 12th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo) ◽

Hybrid Simulation of Electromagnetic field of the On-Chip Clock Distribution Network

10.1109/emccompo48512.2019.9097106 ◽

2019 ◽

Author(s):

Liu Hui-Min ◽

Su Tao

Keyword(s):

Electromagnetic Field ◽

Distribution Network ◽

Hybrid Simulation ◽

Clock Distribution ◽

On Chip