Evaluation of Cache-Based Memory Hierarchy for HEVC Video Decoding

Author(s):  
Garrenlus de Souza ◽  
Sergio Bampi ◽  
Arthur Cerveira ◽  
Bruno Zatt ◽  
Felipe Sampaio
2018 ◽  
Vol 175 ◽  
pp. 02009
Author(s):  
Carleton DeTar ◽  
Steven Gottlieb ◽  
Ruizi Li ◽  
Doug Toussaint

With recent developments in parallel supercomputing architecture, many core, multi-core, and GPU processors are now commonplace, resulting in more levels of parallelism, memory hierarchy, and programming complexity. It has been necessary to adapt the MILC code to these new processors starting with NVIDIA GPUs, and more recently, the Intel Xeon Phi processors. We report on our efforts to port and optimize our code for the Intel Knights Landing architecture. We consider performance of the MILC code with MPI and OpenMP, and optimizations with QOPQDP and QPhiX. For the latter approach, we concentrate on the staggered conjugate gradient and gauge force. We also consider performance on recent NVIDIA GPUs using the QUDA library.


1995 ◽  
Vol 23 (3) ◽  
pp. 28
Author(s):  
Daniel Tabak
Keyword(s):  

Author(s):  
Shinobu Fujita ◽  
Hiroki Noguchi ◽  
Kazutaka Ikegami ◽  
Susumu Takeda ◽  
Kumiko Nomura ◽  
...  
Keyword(s):  

2012 ◽  
Vol 22 (03) ◽  
pp. 1250007 ◽  
Author(s):  
PEDRO RODRÍGUEZ ◽  
MARÍA CECILIA RIVARA ◽  
ISAAC D. SCHERSON

A novel parallelization of the Lepp-bisection algorithm for triangulation refinement on multicore systems is presented. Randomization and wise use of the memory hierarchy are shown to highly improve algorithm performance. Given a list of selected triangles to be refined, random selection of candidates together with pre-fetching of Lepp-submeshes lead to a scalable and efficient multi-core parallel implementation. The quality of the refinement is shown to be preserved.


2002 ◽  
Vol 12 (8) ◽  
pp. 678-687 ◽  
Author(s):  
Yingwei Chen ◽  
Zhun Zhong ◽  
Tse-Hua Lan ◽  
S. Peng ◽  
K. van Zon
Keyword(s):  

Author(s):  
Jae-Jin Lee ◽  
KyungJin Byun ◽  
NakWoong Eum
Keyword(s):  

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