A hardware architecture for accelerating neuromorphic vision algorithms

Author(s):  
A. Al Maashri ◽  
M. DeBole ◽  
C.-L. Yu ◽  
V. Narayanan ◽  
C. Chakrabarti
2016 ◽  
Vol 12 (2) ◽  
pp. 188-197
Author(s):  
A yahoo.com ◽  
Aumalhuda Gani Abood aumalhuda ◽  
A comp ◽  
Dr. Mohammed A. Jodha ◽  
Dr. Majid A. Alwan

Author(s):  
Matheus Jahnke ◽  
Jones Goebel ◽  
Daniel Palomino ◽  
Guilherme Correa ◽  
Luciano Agostini ◽  
...  

2021 ◽  
Vol 12 (1) ◽  
Author(s):  
Qian-Bing Zhu ◽  
Bo Li ◽  
Dan-Dan Yang ◽  
Chi Liu ◽  
Shun Feng ◽  
...  

AbstractThe challenges of developing neuromorphic vision systems inspired by the human eye come not only from how to recreate the flexibility, sophistication, and adaptability of animal systems, but also how to do so with computational efficiency and elegance. Similar to biological systems, these neuromorphic circuits integrate functions of image sensing, memory and processing into the device, and process continuous analog brightness signal in real-time. High-integration, flexibility and ultra-sensitivity are essential for practical artificial vision systems that attempt to emulate biological processing. Here, we present a flexible optoelectronic sensor array of 1024 pixels using a combination of carbon nanotubes and perovskite quantum dots as active materials for an efficient neuromorphic vision system. The device has an extraordinary sensitivity to light with a responsivity of 5.1 × 107 A/W and a specific detectivity of 2 × 1016 Jones, and demonstrates neuromorphic reinforcement learning by training the sensor array with a weak light pulse of 1 μW/cm2.


Author(s):  
Parastoo Soleimani ◽  
David W. Capson ◽  
Kin Fun Li

AbstractThe first step in a scale invariant image matching system is scale space generation. Nonlinear scale space generation algorithms such as AKAZE, reduce noise and distortion in different scales while retaining the borders and key-points of the image. An FPGA-based hardware architecture for AKAZE nonlinear scale space generation is proposed to speed up this algorithm for real-time applications. The three contributions of this work are (1) mapping the two passes of the AKAZE algorithm onto a hardware architecture that realizes parallel processing of multiple sections, (2) multi-scale line buffers which can be used for different scales, and (3) a time-sharing mechanism in the memory management unit to process multiple sections of the image in parallel. We propose a time-sharing mechanism for memory management to prevent artifacts as a result of separating the process of image partitioning. We also use approximations in the algorithm to make hardware implementation more efficient while maintaining the repeatability of the detection. A frame rate of 304 frames per second for a $$1280 \times 768$$ 1280 × 768 image resolution is achieved which is favorably faster in comparison with other work.


Author(s):  
Matheus B. R. Cardoso ◽  
Samuel S. da Silva ◽  
Lucas G. Nardo ◽  
Roberto M. Passos ◽  
Erivelton G. Nepomuceno ◽  
...  

Sign in / Sign up

Export Citation Format

Share Document