A novel phase detector for PAM-4 clock recovery in high speed serial links

2004 ◽  
Author(s):  
Kahn Li Lim ◽  
Z. Zilic
Keyword(s):  
High Speed ◽  
Clock Recovery ◽  
Phase Detector ◽  
Serial Links

A High-Speed Low-Voltage Phase Detector for Clock Recovery From NRZ Data

2007 ◽  
Vol 54 (8) ◽  
pp. 1626-1635 ◽  
Author(s):  
Francesco Centurelli ◽  
Giuseppe Scotti ◽  
Alessandro Trifiletti
Keyword(s):  
High Speed ◽  
Low Voltage ◽  
Clock Recovery ◽  
Phase Detector ◽  
Voltage Phase

Line coding methods for high speed serial links

2015 ◽  
Vol 2015 (1) ◽  
pp. 000318-000323 ◽  
Author(s):  
Abdelaziz Goulahsen ◽  
Julien Saadé ◽  
Frédéric Pétrot
Keyword(s):  
Transfer Rate ◽  
High Speed ◽  
Clock Recovery ◽  
Link Quality ◽  
Serial Links ◽  
Overhead Line ◽  
Run Length ◽  
Baseline Wander ◽  
The Difference

A line coding for high speed serial transmission is defined by two major characteristics: the maximum guaranteed run length (RL) which is the number of consecutive identical bits, and the running disparity (RD or DC-Balance) which is the difference between the number of 'zeroes' and 'ones' in a frame. Both should be bounded to a certain limit, RL to ensure reliable clock recovery and RD to limit baseline wander. Another important parameter is the overhead predictability. This parameter may be critical for applications that need a regular synchronization but for other applications, especially if the variable transfer rate is handled by the upper layer protocol, a statistical value of this parameter is good enough. In this paper, we propose two programmable line codings which bound RL and RD with fixed or variable overhead. The resulting overhead for the line coding we propose is shown to be the lowest among the existing methods, as much as to 10 times lower than well-known encoding methods. The fixed overhead line coding is based on a generalization of the polarity bit approach and can be dynamically adapted to link quality and the environment. First we propose a line coding which bounds the RL, and then we propose another one which bounds the RD. We end up by combining both methods to build a DC-balanced and Run Length limited line coding.

scholarly journals New bang-bang phase detectors for high-speed serial links

2021 ◽  
Author(s):  
Jiwang Li
Keyword(s):  
High Speed ◽  
Phase Detector ◽  
Linear Phase ◽  
Serial Links ◽  
Pump Frequency ◽  
Fast Acquisition ◽  
Phase Detectors ◽  
A Charge ◽  
Frequency Detector ◽  
Regenerative Phase

Bang-bang phase detector studies were carried out in this thesis. Based on the comparison of linear and non-linear phase detectors, a hybrid phase detector was proposed. It possesses the characteristics of two-XOR phase detectors and improved bang-bang phase detectors. PLLs with the proposed hybrid phase detector possess low timing jitter in lock states and a fast locking process. The effectiveness of the proposed hybrid phase detector was quantified by comparing the performance of three PLLs with identical loop components but different phase detectors. A new bang-bang phase detector with regenerative DFFs was also proposed. The regenerative bang-bang phase detector ensures a fast acquisition of incoming clocks. The effectiveness of the regenerative phase detector was assessed in a 2GHz PLL. A 1X bang-bang phase detector was proposed also. Compared to a 2X bang-bang phase detector, PLLs with a 1X bang-bang phase detector offer faster locking. A DFF frequency detector and a charge-pump frequency detector were also proposed. Both effectively detect the frequency difference.

scholarly journals New bang-bang phase detectors for high-speed serial links

2021 ◽  
Author(s):  
Jiwang Li
Keyword(s):  
High Speed ◽  
Phase Detector ◽  
Linear Phase ◽  
Serial Links ◽  
Pump Frequency ◽  
Fast Acquisition ◽  
Phase Detectors ◽  
A Charge ◽  
Frequency Detector ◽  
Regenerative Phase

Bang-bang phase detector studies were carried out in this thesis. Based on the comparison of linear and non-linear phase detectors, a hybrid phase detector was proposed. It possesses the characteristics of two-XOR phase detectors and improved bang-bang phase detectors. PLLs with the proposed hybrid phase detector possess low timing jitter in lock states and a fast locking process. The effectiveness of the proposed hybrid phase detector was quantified by comparing the performance of three PLLs with identical loop components but different phase detectors. A new bang-bang phase detector with regenerative DFFs was also proposed. The regenerative bang-bang phase detector ensures a fast acquisition of incoming clocks. The effectiveness of the regenerative phase detector was assessed in a 2GHz PLL. A 1X bang-bang phase detector was proposed also. Compared to a 2X bang-bang phase detector, PLLs with a 1X bang-bang phase detector offer faster locking. A DFF frequency detector and a charge-pump frequency detector were also proposed. Both effectively detect the frequency difference.

Supply Noise Induced Jitter Reduction in Package Power Distributed Networks for 28 Gbps High Speed Serial Links

2018 ◽  
Author(s):  
Sheng-Fan Yang ◽  
Hunter Lin ◽  
Martin Sun ◽  
Steve S.A. Wan
Keyword(s):  
High Speed ◽  
Distributed Networks ◽  
Serial Links ◽  
Supply Noise

High-speed clock recovery unit based on a phase aligner

2003 ◽  
Author(s):  
Efrain Tejera ◽  
Roberto Esper-Chain ◽  
Felix Tobajas ◽  
Valentin De Armas ◽  
Roberto Sarmiento
Keyword(s):  
High Speed ◽  
Clock Recovery ◽  
Recovery Unit

Phase detector for data-clock recovery circuit

2002 ◽  
Vol 38 (4) ◽  
pp. 161 ◽  
Author(s):  
A. Hati ◽  
M. Ghosh ◽  
B.C. Sarkar
Keyword(s):  
Clock Recovery ◽  
Phase Detector
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