scholarly journals New bang-bang phase detectors for high-speed serial links

2021 ◽  
Author(s):  
Jiwang Li
Keyword(s):  
High Speed ◽  
Phase Detector ◽  
Linear Phase ◽  
Serial Links ◽  
Pump Frequency ◽  
Fast Acquisition ◽  
Phase Detectors ◽  
A Charge ◽  
Frequency Detector ◽  
Regenerative Phase

Bang-bang phase detector studies were carried out in this thesis. Based on the comparison of linear and non-linear phase detectors, a hybrid phase detector was proposed. It possesses the characteristics of two-XOR phase detectors and improved bang-bang phase detectors. PLLs with the proposed hybrid phase detector possess low timing jitter in lock states and a fast locking process. The effectiveness of the proposed hybrid phase detector was quantified by comparing the performance of three PLLs with identical loop components but different phase detectors. A new bang-bang phase detector with regenerative DFFs was also proposed. The regenerative bang-bang phase detector ensures a fast acquisition of incoming clocks. The effectiveness of the regenerative phase detector was assessed in a 2GHz PLL. A 1X bang-bang phase detector was proposed also. Compared to a 2X bang-bang phase detector, PLLs with a 1X bang-bang phase detector offer faster locking. A DFF frequency detector and a charge-pump frequency detector were also proposed. Both effectively detect the frequency difference.

scholarly journals New bang-bang phase detectors for high-speed serial links

2021 ◽  
Author(s):  
Jiwang Li
Keyword(s):  
High Speed ◽  
Phase Detector ◽  
Linear Phase ◽  
Serial Links ◽  
Pump Frequency ◽  
Fast Acquisition ◽  
Phase Detectors ◽  
A Charge ◽  
Frequency Detector ◽  
Regenerative Phase

Bang-bang phase detector studies were carried out in this thesis. Based on the comparison of linear and non-linear phase detectors, a hybrid phase detector was proposed. It possesses the characteristics of two-XOR phase detectors and improved bang-bang phase detectors. PLLs with the proposed hybrid phase detector possess low timing jitter in lock states and a fast locking process. The effectiveness of the proposed hybrid phase detector was quantified by comparing the performance of three PLLs with identical loop components but different phase detectors. A new bang-bang phase detector with regenerative DFFs was also proposed. The regenerative bang-bang phase detector ensures a fast acquisition of incoming clocks. The effectiveness of the regenerative phase detector was assessed in a 2GHz PLL. A 1X bang-bang phase detector was proposed also. Compared to a 2X bang-bang phase detector, PLLs with a 1X bang-bang phase detector offer faster locking. A DFF frequency detector and a charge-pump frequency detector were also proposed. Both effectively detect the frequency difference.

A 1/4-RATE LINEAR PHASE DETECTOR FOR HIGH SPEED PLL-BASED CLOCK AND DATA RECOVERY CIRCUIT

2014 ◽  
Vol 23 (05) ◽  
pp. 1450072 ◽  
Author(s):  
SOMAYEH ADIBIFARD ◽  
SEYYED HASSAN MOUSAVI ◽  
SOHEYL ZIABAKHSH ◽  
MUSTAPHA C. E. YAGOUB
Keyword(s):  
Power Consumption ◽  
Delay Time ◽  
High Speed ◽  
Clock And Data Recovery ◽  
Cmos Technology ◽  
Data Recovery ◽  
Phase Detector ◽  
Linear Phase ◽  
Lower Power ◽  
Reference Signals

A novel 1/4-rate clock phase detector (PD) structure for phase locked loop (PLL)-based clock and data recovery (CDR) is proposed. In this topology, the retimed data is generated within the circuit and no extra circuit is required. Furthermore, the error and reference signals are independent of delay time through gates and thus, no extra replica circuit is needed to compensate such delay. Designed in a 0.18-μm CMOS technology, the proposed 10 Gb/s PD consumes 30 mA from a 1.8 V supply, resulting in a lower power consumption for high-speed applications compared to conventional topologies.

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