Adaptive Channel Buffers in On-Chip Interconnection Networks— A Power and Performance Analysis

2008 ◽  
Vol 57 (9) ◽  
pp. 1169-1181 ◽  
Author(s):  
Avinash Karanth Kodi ◽  
Ashwini Sarathy ◽  
Ahmed Louri
Keyword(s):  
Performance Analysis ◽  
Interconnection Networks ◽  
And Performance ◽  
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scholarly journals Model of Network-on-Chip routers and performance analysis

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pp. 986-993 ◽  
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Xiaoguo Dong ◽  
Siqing Gan ◽  
Weimin Zheng
Keyword(s):  
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Network On Chip ◽  
And Performance ◽  
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scholarly journals Design Trade off and Performance Analysis of Router Architectures in Network-on-Chip

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pp. 421-426
Author(s):  
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Hassan Nazeer Chaudhry ◽  
Sadia Azam ◽  
Naveed Khan baloch
Keyword(s):  
Performance Analysis ◽  
Network On Chip ◽  
Trade Off ◽  
And Performance ◽  
On Chip
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