Sleep Transistor Sizing for Leakage Power Minimization Considering Temporal Correlation

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2010.2046812 ◽

2010 ◽

Vol 29 (8) ◽

pp. 1285-1289 ◽

Author(s):

De-Shiuan Chiou ◽

Yu-Ting Chen ◽

Da-Cheng Juan ◽

Shih-Chieh Chang

Keyword(s):

Temporal Correlation ◽

Leakage Power ◽

Power Minimization ◽

Transistor Sizing

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Fine-Grained Sleep Transistor Sizing Algorithm for Leakage Power Minimization

2007 44th ACM/IEEE Design Automation Conference ◽

10.1109/dac.2007.375129 ◽

2007 ◽

Author(s):

De-Shiuan Chiou ◽

Da-Cheng Juan ◽

Yu-Ting Chen ◽

Shih-Chieh Chang

Keyword(s):

Leakage Power ◽

Power Minimization ◽

Fine Grained ◽

Transistor Sizing

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Sleep Transistor Sizing for Leakage Power Minimization Considering Charge Balancing

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2008.2001247 ◽

2009 ◽

Vol 17 (9) ◽

pp. 1330-1334 ◽

Author(s):

De-Shiuan Chiou ◽

Shih-Hsin Chen ◽

Shih-Chieh Chang

Keyword(s):

Leakage Power ◽

Power Minimization ◽

Transistor Sizing ◽

Charge Balancing

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Neural network based optimization of CMOS transistor sizing for leakage power minimization

2012 International Conference on Innovations in Information Technology (IIT) ◽

10.1109/innovations.2012.6207724 ◽

2012 ◽

Author(s):

Omar Banimelhem ◽

Rami Bani Hani

Keyword(s):

Neural Network ◽

Leakage Power ◽

Power Minimization ◽

Transistor Sizing ◽

Cmos Transistor

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Fine-grained sleep transistor sizing algorithm for leakage power minimization

2007 44th ACM/IEEE Design Automation Conference ◽

10.1145/1278480.1278502 ◽

2007 ◽

Author(s):

De-Shiuan Chiou ◽

Da-Cheng Juan ◽

Yu-Ting Chen ◽

Shih-Chieh Chang

Keyword(s):

Leakage Power ◽

Power Minimization ◽

Fine Grained ◽

Transistor Sizing

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Leakage Power Minimization of Nanoscale CMOS Circuits via Non-Critical Path Transistor Sizing

2006 13th IEEE International Conference on Electronics, Circuits and Systems ◽

10.1109/icecs.2006.379631 ◽

2006 ◽

Author(s):

Bo Fu ◽

Paul Ampadu

Keyword(s):

Critical Path ◽

Leakage Power ◽

Cmos Circuits ◽

Power Minimization ◽

Nanoscale Cmos ◽

Transistor Sizing

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The epsilon-approximation to discrete VT assignment for leakage power minimization

Proceedings of the 2009 International Conference on Computer-Aided Design - ICCAD '09 ◽

10.1145/1687399.1687453 ◽

2009 ◽

Author(s):

Yujia Feng ◽

Shiyan Hu

Keyword(s):

Leakage Power ◽

Power Minimization

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Leakage Power Minimization

Low-Power VLSI Circuits and Systems ◽

10.1007/978-81-322-1937-8_9 ◽

2014 ◽

pp. 261-302

Author(s):

Ajit Pal

Keyword(s):

Leakage Power ◽

Power Minimization

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Dynamic and Leakage Power Minimization with Loop Voltage Scheduling and Assignment

2008 IEEE/IFIP International Conference on Embedded and Ubiquitous Computing ◽

10.1109/euc.2008.90 ◽

2008 ◽

Author(s):

Meikang Qiu ◽

Jiande Wu ◽

Jingtong Hu ◽

Yi He ◽

Edwin H.-M. Sha

Keyword(s):

Leakage Power ◽

Power Minimization

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Optimal Transistor Sizing of Full-Adder Block to Reduce Standby Leakage Power

Communications in Computer and Information Science - VLSI Design and Test ◽

10.1007/978-981-13-5950-7_8 ◽

2019 ◽

pp. 88-99

Author(s):

Prateek Gupta ◽

Shubham Kumar ◽

Zia Abbas

Keyword(s):

Leakage Power ◽

Transistor Sizing

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A Genetic Algorithm Based Input State Assignment Technique for Leakage Power Minimization during Combinational Logic Synthesis

15th International Conference on Advanced Computing and Communications (ADCOM 2007) ◽

10.1109/adcom.2007.33 ◽

2007 ◽

Author(s):

Saurabh Chaudhury ◽

Ansuman Prusty ◽

Santanu Chattopadhyay

Keyword(s):

Genetic Algorithm ◽

Logic Synthesis ◽

Leakage Power ◽

Input State ◽

Combinational Logic ◽

Power Minimization ◽

State Assignment

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