Optimal Transistor Sizing of Full-Adder Block to Reduce Standby Leakage Power

2019 ◽  
pp. 88-99
Author(s):  
Prateek Gupta ◽  
Shubham Kumar ◽  
Zia Abbas
Keyword(s):  
Full Adder ◽  
Leakage Power ◽  
Transistor Sizing

Fine-Grained Sleep Transistor Sizing Algorithm for Leakage Power Minimization

2007 ◽  
Author(s):  
De-Shiuan Chiou ◽  
Da-Cheng Juan ◽  
Yu-Ting Chen ◽  
Shih-Chieh Chang
Keyword(s):  
Leakage Power ◽  
Power Minimization ◽  
Fine Grained ◽  
Transistor Sizing

scholarly journals Design and Performasnce Analysis of Hybrid Full Adder Using Finfet 40nm Technology

2019 ◽  
Vol 8 (6) ◽  
pp. 4521-4525
Keyword(s):  
Performance Analysis ◽  
Energy Efficient ◽  
Full Adder ◽  
Propagation Delay ◽  
Leakage Power ◽  
Drive Current ◽  
Internal Logic ◽  
Low Leakage ◽  
Cadence Tool ◽  
Power And Energy

Designing a low power and energy efficient circuits in FinFET technology is of great Challenge. This paper presents the internal logic structure and circuit operation using the devices, CMOS and FinFETs for designing the hybrid adder cells. At transistor level, CMOS and FinFET based hybrid full adder (HFA) and improved hybrid full adder (IHFA) is designed. Simulations are carried out using the cadence tool in UMC 40nm and the performance analysis of these HFA and IHFA are compared with the 40nm FinFET technology. It is observed that IHFA is better when compared with the HFA in terms of propagation delay, power consumption and energy delay product. IHFA achieves the higher drive current and low leakage power for better mobility and transistor scaling as compared with HFA.

scholarly journals Estimation of Leakage Power and Delay in CMOS Circuits

2020 ◽  
Vol 4 (7) ◽  
pp. 14-19
Author(s):  
Mohasinul Huq N Md ◽  
Mohan Das S ◽  
Bilal N Md
Keyword(s):  
Power Dissipation ◽  
Supply Voltage ◽  
Full Adder ◽  
Cmos Technology ◽  
Propagation Delay ◽  
Leakage Power ◽  
Nand Gate ◽  
High Threshold ◽  
Cmos Circuits ◽  
Low Leakage

This paper presents an estimation of leakage power and delay for 1-bit Full Adder (FA)designed which is based on Leakage Control Transistor (LCT) NAND gates as basic building block. The main objective is to design low leakage full adder circuit with the help of low and high threshold transistors. The simulations for the designed circuits performed in cadence virtuoso tool with 45 nm CMOS technology at a supply voltage of 0.9 Volts. Further, analysis of effect of parametric variation on leakage current and propagation delay in CMOS circuits is performed. The saving in leakage power dissipation for LCT NAND_HVT gate is up to 72.33% and 45.64% when compared to basic NAND and LCT NAND gate. Similarly for 1-bit full adder the saving is up to 90.9% and 40.08% when compared to basic NAND FA and LCT NAND.

A New Keeper Domino Logic Based Full Adder for High Speed Arithmetic Circuits

2020 ◽  
Vol 12 ◽  
Author(s):  
Deepika Bansal ◽  
Bal Chand Nagar ◽  
Ajay Kumar ◽  
Brahamdeo Prasad Singh
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
High Efficiency ◽  
Dynamic Logic ◽  
Full Adder ◽  
Leakage Power ◽  
Low Leakage ◽  
Dynamic Circuits ◽  
Power Delay Product ◽  
Domino Circuits

Objective: A new efficient keeper circuit has been proposed in this article for achieving low leakage power consumption and to improve power delay product of the dynamic logic using carbon nanotube MOSFET. Method: As a benchmark, an one-bit adder has been designed and characterized with both technologies Si-MOSFET and CN-MOSFET using proposed and existing dynamic circuits. Furthermore, a comparison has been made to demonstrate the superiority of CN-MOSFET technology with Synopsys HSPICE tool for multiple bit adders available in the literature. Result: The simulation results show that the proposed keeper circuit provides lower static and dynamic power consumption up to 57 and 40% respectively, as compared to the domino circuits using 32nm CN-MOSFET technology provided by Stanford University. Moreover, the proposed keeper configuration provides better performance using SiMOSFET and CN-MOSFET technologies. Conclusion: A comparison of the proposed keeper with previously published designs is also given in terms of power consumption, delay and power delay product with the improvement up to 75, 18 and 50% respectively. The proposed circuit uses only two transistors, so it requires less area and gives high efficiency.

A HIGH-LEVEL TECHNIQUE FOR ESTIMATION AND OPTIMIZATION OF LEAKAGE POWER FOR FULL ADDER

2013 ◽  
Vol 12 (02) ◽  
pp. 1350011
Author(s):  
JAYRAM SHRIVAS ◽  
SHYAM AKASHE ◽  
NITESH TIWARI
Keyword(s):  
Leakage Current ◽  
Power Supply ◽  
Low Voltage ◽  
Full Adder ◽  
Leakage Power ◽  
Power Gating ◽  
Sleep Transistors ◽  
Power Application ◽  
High Level ◽  
Standby Mode

Optimization of power is a very important issue in low-voltage and low-power application. In this paper, we have proposed power gating technique to reduce leakage current and leakage power of one-bit full adder. In this power gating technique, we use two sleep transistors i.e., PMOS and NMOS. PMOS sleep transistor is inserted between power supply and pull up network. And NMOS sleep transistor is inserted between pull down network and ground terminal. These sleep transistors (PMOS and NMOS) are turned on when the circuit is working in active mode. And sleep transistors (PMOS and NMOS) are turned off when circuit is working in standby mode. We have simulated one-bit full adder and compared with the power gating technique using cadence virtuoso tool in 45 nm technology at 0.7 V at 27°C. By applying this technique, we have reduced leakage current from 2.935 pA to 1.905 pA and leakage power from 25.04μw to 9.233μw. By using this technique, we have reduced leakage power up to 63.12%.

scholarly journals Forced stack sleep transistor (FORTRAN): A new leakage current reduction approach in CMOS based circuit designing

2021 ◽  
Vol 34 (2) ◽  
pp. 259-280
Author(s):  
Sankit Kassa ◽  
Neeraj Misra ◽  
Rajendra Nagaria
Keyword(s):  
Low Power ◽  
Leakage Current ◽  
Power Efficiency ◽  
High Performance ◽  
Low Voltage ◽  
Full Adder ◽  
Leakage Power ◽  
Modes Of Operation ◽  
Power Circuit ◽  
Current Reduction

Reduction in leakage current has become a significant concern in nanotechnology-based low-power, low-voltage, and high-performance VLSI applications. This research article discusses a new low-power circuit design the approach of FORTRAN (FORced stack sleep TRANsistor), which decreases the leakage power efficiency in the CMOS-based circuit outline in VLSI domain. FORTRAN approach reduces leakage current in both active as well as standby modes of operation. Furthermore, it is not time intensive when the circuit goes from active mode to standby mode and vice-versa. To validate the proposed design approach, experiments are conducted in the Tanner EDA tool of mentor graphics bundle on projected circuit designs for the full adder, a chain of 4-inverters, and 4- bit multiplier designs utilizing 180nm, 130nm, and 90nm TSMC technology node. The outcomes obtained show the result of a 95-98% vital reduction in leakage power as well as a 15-20% reduction in dynamic power with a minor increase in delay. The result outcomes are compared for accuracy with the notable design approaches that are accessible for both active and standby modes of operation.

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