Timing-Aware Layer Assignment for Advanced Process Technologies Considering Via Pillars

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2021.3100296 ◽

2021 ◽

pp. 1-1

Author(s):

Genggeng Liu ◽

Xinghai Zhang ◽

Wenzhong Guo ◽

Xing Huang ◽

Wen-Hao Liu ◽

...

Keyword(s):

Layer Assignment

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Chip layer assignment method for analytical placement of 3D ICs

Journal of Computer Applications ◽

10.3724/sp.j.1087.2013.01548 ◽

2013 ◽

Vol 33 (6) ◽

pp. 1548-1552

Author(s):

Wenchao GAO ◽

Qiang ZHOU ◽

Xu QIAN ◽

Yici CAI

Keyword(s):

Assignment Method ◽

3D Ics ◽

Layer Assignment

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Algorithmic implementation of deep learning layer assignment in edge computing based smart city environment

Computers & Electrical Engineering ◽

10.1016/j.compeleceng.2020.106909 ◽

2021 ◽

Vol 89 ◽

pp. 106909

Author(s):

Kyuchang Lee ◽

Bhagya Nathali Silva ◽

Kijun Han

Keyword(s):

Deep Learning ◽

Edge Computing ◽

City Environment ◽

Layer Assignment

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Latency constraint guided buffer sizing and layer assignment for clock trees with useful skew

Proceedings of the 24th Asia and South Pacific Design Automation Conference on - ASPDAC '19 ◽

10.1145/3287624.3287681 ◽

2019 ◽

Author(s):

Necati Uysal ◽

Wen-Hao Liu ◽

Rickard Ewetz

Keyword(s):

Buffer Sizing ◽

Layer Assignment

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Density-reduction-oriented layer assignment for rectangle escape routing

Proceedings of the great lakes symposium on VLSI - GLSVLSI '12 ◽

10.1145/2206781.2206848 ◽

2012 ◽

Author(s):

Jin-Tai Yan ◽

Jun-Min Chung ◽

Zhi-Wei Chen

Keyword(s):

Density Reduction ◽

Layer Assignment ◽

Escape Routing ◽

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Direction-constrained layer assignment for rectangle escape routing

2012 IEEE International SOC Conference ◽

10.1109/socc.2012.6398357 ◽

2012 ◽

Author(s):

Jin-Tai Yan ◽

Zhi-Wei Chen

Keyword(s):

Layer Assignment ◽

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Minimum crosstalk layer assignment in a three layer HVH channel routing based on linear pseudo Boolean optimization

ICM 2000. Proceedings of the 12th International Conference on Microelectronics. (IEEE Cat. No.00EX453) ◽

10.1109/icm.2000.916407 ◽

2002 ◽

Author(s):

Kyoung Jhang

Keyword(s):

Channel Routing ◽

Layer Assignment ◽

Boolean Optimization

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Removal of Intersection for Multi-net Multi-pin Routing Problem with Layer Assignment

2010 Second International Conference on Computer Engineering and Applications ◽

10.1109/iccea.2010.57 ◽

2010 ◽

Author(s):

Subhra Sundar Goswami

Keyword(s):

Routing Problem ◽

Layer Assignment

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Layer assignment for VLSI interconnect delay minimization

Microelectronics Journal ◽

10.1016/0026-2692(90)90083-f ◽

1990 ◽

Vol 21 (4) ◽

pp. 62-63

Keyword(s):

Delay Minimization ◽

Interconnect Delay ◽

Layer Assignment

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Memory binding and layer assignment for high-level synthesis of 3D ICs

2012 IEEE Asia Pacific Conference on Circuits and Systems ◽

10.1109/apccas.2012.6419111 ◽

2012 ◽

Author(s):

Yi-Chun Yen ◽

Jhih-Kai Yang ◽

Wei-Kai Cheng

Keyword(s):

High Level Synthesis ◽

Memory Binding ◽

3D Ics ◽

Layer Assignment ◽

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Incremental Layer Assignment Driven by an External Signoff Timing Engine

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2016.2638450 ◽

2017 ◽

Vol 36 (7) ◽

pp. 1126-1139 ◽

Author(s):

Vinicius Livramento ◽

Derong Liu ◽

Salim Chowdhury ◽

Bei Yu ◽

Xiaoqing Xu ◽

...

Keyword(s):

Layer Assignment

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