Proceedings of the great lakes symposium on VLSI - GLSVLSI '12
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Published By ACM Press

9781450312448

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Density-reduction-oriented layer assignment for rectangle escape routing

Proceedings of the great lakes symposium on VLSI - GLSVLSI '12 ◽

10.1145/2206781.2206848 ◽

2012 ◽

Cited By ~ 1

Author(s):

Jin-Tai Yan ◽

Jun-Min Chung ◽

Zhi-Wei Chen

Keyword(s):

Density Reduction ◽

Layer Assignment ◽

Escape Routing ◽

Oriented Layer

Multiplexed switch box architecture in three-dimensional FPGAs to reduce silicon area and improve TSV usage

Proceedings of the great lakes symposium on VLSI - GLSVLSI '12 ◽

10.1145/2206781.2206855 ◽

2012 ◽

Cited By ~ 1

Author(s):

Marzieh Morshedzadeh Morshedzadeh ◽

Ali Jahanian

Keyword(s):

Three Dimensional ◽

Silicon Area

Unifying functional and parametric timing verification

Proceedings of the great lakes symposium on VLSI - GLSVLSI '12 ◽

10.1145/2206781.2206816 ◽

2012 ◽

Author(s):

Luis Guerra e Silva

Keyword(s):

Timing Verification

STEP

Proceedings of the great lakes symposium on VLSI - GLSVLSI '12 ◽

10.1145/2206781.2206862 ◽

2012 ◽

Author(s):

Pranav Yeolekar ◽

Rishad A. Shafik ◽

Jimson Mathew ◽

Dhiraj K. Pradhan ◽

Saraju P. Mohanty

A low-power all-digital GFSK demodulator with robust clock data recovery

Proceedings of the great lakes symposium on VLSI - GLSVLSI '12 ◽

10.1145/2206781.2206813 ◽

2012 ◽

Cited By ~ 4

Author(s):

Pengpeng Chen ◽

Bo Zhao ◽

Rong Luo ◽

Huazhong Yang

Keyword(s):

Low Power ◽

Data Recovery ◽

Clock Data Recovery

Sustainable multi-core architecture with on-chip wireless links

Proceedings of the great lakes symposium on VLSI - GLSVLSI '12 ◽

10.1145/2206781.2206845 ◽

2012 ◽

Cited By ~ 1

Author(s):

Jacob Murray ◽

John Klingner ◽

Partha P. Pande ◽

Behrooz Shirazi

Keyword(s):

Wireless Links ◽

On Chip

Share memory aware scheduler

Proceedings of the great lakes symposium on VLSI - GLSVLSI '12 ◽

10.1145/2206781.2206852 ◽

2012 ◽

Cited By ~ 3

Author(s):

Xi Li ◽

Gangyong Jia ◽

Yun Chen ◽

Zongwei Zhu ◽

Xuehai Zhou

Self adaptive body biasing scheme for leakage power reduction in nanoscale CMOS circuit

Proceedings of the great lakes symposium on VLSI - GLSVLSI '12 ◽

10.1145/2206781.2206811 ◽

2012 ◽

Cited By ~ 1

Author(s):

Jing Yang ◽

Yong-bin Kim

Keyword(s):

Power Reduction ◽

Leakage Power ◽

Cmos Circuit ◽

Nanoscale Cmos ◽

Body Biasing ◽

Self Adaptive

Synchronization scheme for brick-based rotary oscillator arrays

Proceedings of the great lakes symposium on VLSI - GLSVLSI '12 ◽

10.1145/2206781.2206812 ◽

2012 ◽

Cited By ~ 3

Author(s):

Ying Teng ◽

Baris Taskin

Keyword(s):

Oscillator Arrays ◽

Synchronization Scheme

Performance and energy models for memristor-based 1T1R RRAM cell

Proceedings of the great lakes symposium on VLSI - GLSVLSI '12 ◽

10.1145/2206781.2206786 ◽

2012 ◽

Cited By ~ 10

Author(s):

Mahmoud Zangeneh ◽

Ajay Joshi

Keyword(s):

Energy Models

Proceedings of the great lakes symposium on VLSI - GLSVLSI '12Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By ACM Press

Density-reduction-oriented layer assignment for rectangle escape routing

Multiplexed switch box architecture in three-dimensional FPGAs to reduce silicon area and improve TSV usage

Unifying functional and parametric timing verification

STEP

A low-power all-digital GFSK demodulator with robust clock data recovery

Sustainable multi-core architecture with on-chip wireless links

Share memory aware scheduler

Self adaptive body biasing scheme for leakage power reduction in nanoscale CMOS circuit

Synchronization scheme for brick-based rotary oscillator arrays

Performance and energy models for memristor-based 1T1R RRAM cell

Proceedings of the great lakes symposium on VLSI - GLSVLSI '12
Latest Publications