Low power FPGA design using hybrid CMOS-NEMS approach

2007 ◽  
Author(s):  
Yu Zhou ◽  
Shijo Thekkel ◽  
Swarup Bhunia
Keyword(s):  
Low Power ◽  
Fpga Design ◽  
Hybrid Cmos

Very Compact and Efficient 32-Bit AES Core Design Using FPGAs for Small-Footprint Low-Power Embedded Applications

2016 ◽  
Vol 25 (07) ◽  
pp. 1650080 ◽  
Author(s):  
Raed Bani-Hani ◽  
Khaldoon Mhaidat ◽  
Salah Harb
Keyword(s):  
Low Power ◽  
Area Ratio ◽  
Advanced Encryption Standard ◽  
Fpga Design ◽  
Power Efficient ◽  
Aes Algorithm ◽  
Lookup Tables ◽  
Small Footprint ◽  
Embedded Applications

In this paper, a very compact and efficient 32-bit FPGA design for the Advanced Encryption Standard (AES) algorithm is presented. The design is very well suited for small foot-print low-power embedded applications. The design is validated and synthesized using the Xilinx ISE Design Suite. To the best of our knowledge, our design is the most efficient in terms of throughput to area ratio and requires the smallest number of lookup tables (LUTs), logic slices, and registers. It also achieves the highest throughput among designs that do not use DSPs. It is also very power-efficient; it can process more than 10 Gbps/W on Kintex-7 FPGA.

Low-Power High-Speed Small Area Hybrid CMOS Full Adder

2012 ◽  
Vol 2 (1) ◽  
pp. 47 ◽  
Author(s):  
Amit Gupta ◽  
Rasika Dhavse ◽  
RK Sharma
Keyword(s):  
Low Power ◽  
Small Area ◽  
High Speed ◽  
Full Adder ◽  
Hybrid Cmos
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