Low-Latency Double Point Multiplication Architecture Using Differential Addition Chain Over $GF(2^m)$

2019 ◽  
Vol 66 (4) ◽  
pp. 1465-1473 ◽  
Author(s):  
Taha Shahroodi ◽  
Siavash Bayat-Sarmadi ◽  
Hatameh Mosanaei-Boorani
Keyword(s):  
Double Point ◽  
Low Latency ◽  
Point Multiplication ◽  
Addition Chain

A Low-Latency and Low-Complexity Point-Multiplication in ECC

2018 ◽  
Vol 65 (9) ◽  
pp. 2869-2877 ◽  
Author(s):  
Raziyeh Salarifard ◽  
Siavash Bayat-Sarmadi ◽  
Hatameh Mosanaei-Boorani
Keyword(s):  
Low Complexity ◽  
Low Latency ◽  
Point Multiplication

scholarly journals Random Euclidean Addition Chain Generation and Its Application to Point Multiplication

2010 ◽  
pp. 238-261 ◽  
Author(s):  
Fabien Herbaut ◽  
Pierre-Yvan Liardet ◽  
Nicolas Méloni ◽  
Yannick Téglia ◽  
Pascal Véron
Keyword(s):  
Point Multiplication ◽  
Addition Chain

An Efficient Low-Latency Point-Multiplication Over Curve25519

2019 ◽  
Vol 66 (10) ◽  
pp. 3854-3862 ◽  
Author(s):  
Raziyeh Salarifard ◽  
Siavash Bayat-Sarmadi
Keyword(s):  
Low Latency ◽  
Point Multiplication

scholarly journals High Performance and Low Latency ECC Processor for Cryptography

2021 ◽  
pp. 24-30
Author(s):  
Mohan Rao Thokala
Keyword(s):  
Elliptic Curve ◽  
Elliptic Curve Cryptography ◽  
Field Programmable Gate Array ◽  
High Performance ◽  
Low Latency ◽  
Data Dependency ◽  
Drastic Reduction ◽  
Point Multiplication ◽  
Field Programmable ◽  
Xilinx Fpga

Elliptic curve cryptography processor implemented for point multiplication on field programmable gate array. Segmented pipelined full-precision multiplier is used to reduce the latency and also data dependency can be avoided by modifying Lopez-Dahab Montgomery PM Algorithm, results in drastic reduction in the number of clock cycles required. The proposed ECC processor is implemented on Xilinx FPGA families i.e. virtex-4, vitrtex-5, virtex-7.single and three multiplier based designs show the fastest performance compared with reported work individually. Our three multiplier based ECC processor implementation is taking the lowest number of clock cycles on FPGA based design processor.

Double Point Compression with Applications to Speeding Up Random Point Multiplication

2007 ◽  
Vol 56 (3) ◽  
pp. 305-313 ◽  
Author(s):  
Majid Khabbazian ◽  
T. Aaron Gulliver ◽  
Vijay K. Bhargava
Keyword(s):  
Double Point ◽  
Random Point ◽  
Point Multiplication ◽  
Point Compression
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