Knowledge-Based Neural Networks for Fast Design Space Exploration of Hybrid Copper-Graphene On-Chip Interconnect Networks

IEEE Transactions on Electromagnetic Compatibility ◽

10.1109/temc.2021.3091714 ◽

2021 ◽

pp. 1-14

Author(s):

Rahul Kumar ◽

S. S. Likith Narayan ◽

Somesh Kumar ◽

Sourajeet Roy ◽

Brajesh Kaushik ◽

...

Keyword(s):

Neural Networks ◽

Design Space Exploration ◽

Design Space ◽

Space Exploration ◽

Knowledge Based ◽

Interconnect Networks ◽

On Chip

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Fast system-level design space exploration for low power configurable multimedia systems-on-chip

15th Annual IEEE International ASIC/SOC Conference ◽

10.1109/asic.2002.1158047 ◽

2003 ◽

Cited By ~ 4

Author(s):

F. Polloni ◽

L. Mazzoni ◽

S. Di Matteo

Keyword(s):

Low Power ◽

Design Space Exploration ◽

Design Space ◽

Space Exploration ◽

Multimedia Systems ◽

System Level ◽

System Level Design ◽

Fast System ◽

Systems On Chip ◽

On Chip

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A flexible network-on-chip simulator for early design space exploration

2008 1st Microsystems and Nanoelectronics Research Conference ◽

10.1109/mnrc.2008.4683371 ◽

2008 ◽

Cited By ~ 9

Author(s):

Cristian Grecu ◽

Andre Ivanov ◽

Resve Saleh ◽

Claudia Rusu ◽

Lorena Anghel ◽

...

Keyword(s):

Design Space Exploration ◽

Design Space ◽

Space Exploration ◽

Network On Chip ◽

Early Design ◽

On Chip

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Design space exploration for robust power delivery in TSV based 3-D systems-on-chip

2012 IEEE International SOC Conference ◽

10.1109/socc.2012.6398327 ◽

2012 ◽

Author(s):

Suhas M. Satheesh ◽

Emre Salman

Keyword(s):

Design Space Exploration ◽

Design Space ◽

Space Exploration ◽

Power Delivery ◽

Systems On Chip ◽

On Chip

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PGOpt: Multi-objective Design Space Exploration Framework for Large-Scale On-Chip Power Grid Design in VLSI SoC using Evolutionary Computing Technique

Microprocessors and Microsystems ◽

10.1016/j.micpro.2020.103440 ◽

2020 ◽

pp. 103440

Author(s):

Sukanta Dey ◽

Sukumar Nandi ◽

Gaurav Trivedi

Keyword(s):

Large Scale ◽

Design Space Exploration ◽

Design Space ◽

Space Exploration ◽

Power Grid ◽

Evolutionary Computing ◽

Computing Technique ◽

Multi Objective ◽

Grid Design ◽

On Chip

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A Design Space Exploration Method for On-Chip Memory System Based on Task Scheduling

2018 IEEE 9th International Conference on Software Engineering and Service Science (ICSESS) ◽

10.1109/icsess.2018.8663909 ◽

2018 ◽

Author(s):

Hongyu Meng ◽

Hongli Meng ◽

Pengfei Ding ◽

Mingxuan Wang ◽

Donglin Wang

Keyword(s):

Task Scheduling ◽

Design Space Exploration ◽

Design Space ◽

Space Exploration ◽

Memory System ◽

On Chip

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Trace-Driven Simulation and Design Space Exploration of Network-on-Chip Topologies on FPGA

2018 8th International Symposium on Embedded Computing and System Design (ISED) ◽

10.1109/ised.2018.8703884 ◽

2018 ◽

Cited By ~ 1

Author(s):

G S Sangeetha ◽

Vignesh Radhakrishnan ◽

Prabhu Prasad ◽

Khyamling Parane ◽

Basavaraj Talawar

Keyword(s):

Design Space Exploration ◽

Design Space ◽

Space Exploration ◽

Network On Chip ◽

On Chip

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Design-Space Exploration and Optimization of an Energy-Efficient and Reliable 3-D Small-World Network-on-Chip

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2016.2604288 ◽

2017 ◽

Vol 36 (5) ◽

pp. 719-732 ◽

Cited By ~ 33

Author(s):

Sourav Das ◽

Janardhan Rao Doppa ◽

Partha Pratim Pande ◽

Krishnendu Chakrabarty

Keyword(s):

Energy Efficient ◽

Design Space Exploration ◽

Design Space ◽

Space Exploration ◽

Small World ◽

Network On Chip ◽

Small World Network ◽

On Chip

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Design space exploration of FPGA-based Deep Convolutional Neural Networks

2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC) ◽

10.1109/aspdac.2016.7428073 ◽

2016 ◽

Cited By ~ 84

Author(s):

Mohammad Motamedi ◽

Philipp Gysel ◽

Venkatesh Akella ◽

Soheil Ghiasi

Keyword(s):

Neural Networks ◽

Convolutional Neural Networks ◽

Design Space Exploration ◽

Design Space ◽

Space Exploration ◽

Deep Convolutional Neural Networks

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POSTER: Design Space Exploration for Performance Optimization of Deep Neural Networks on Shared Memory Accelerators

2017 26th International Conference on Parallel Architectures and Compilation Techniques (PACT) ◽

10.1109/pact.2017.39 ◽

2017 ◽

Cited By ~ 6

Author(s):

Swagath Venkataramani ◽

Jungwook Choi ◽

Vijayalakshmi Srinivasan ◽

Kailash Gopalakrishnan ◽

Leland Chang

Keyword(s):

Neural Networks ◽

Shared Memory ◽

Performance Optimization ◽

Design Space Exploration ◽

Deep Neural Networks ◽

Design Space ◽

Space Exploration

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A design space exploration of transmission-line links for on-chip interconnect

IEEE/ACM International Symposium on Low Power Electronics and Design ◽

10.1109/islped.2011.5993647 ◽

2011 ◽

Cited By ~ 5

Author(s):

Aaron Carpenter ◽

Jianyun Hu ◽

Michael Huang ◽

Hui Wu ◽

Peng Liu

Keyword(s):

Transmission Line ◽

Design Space Exploration ◽

Design Space ◽

Space Exploration ◽

On Chip

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