Fast system-level design space exploration for low power configurable multimedia systems-on-chip

2003 ◽  
Author(s):  
F. Polloni ◽  
L. Mazzoni ◽  
S. Di Matteo
Keyword(s):  
Low Power ◽  
Design Space Exploration ◽  
Design Space ◽  
Space Exploration ◽  
Multimedia Systems ◽  
System Level ◽  
System Level Design ◽  
Fast System ◽  
Systems On Chip ◽  
On Chip

System-Level Design of NoC-Based Dependable Embedded Systems

2014 ◽  
pp. 478-512
Author(s):  
Mihkel Tagel ◽  
Peeter Ellervee ◽  
Gert Jervan
Keyword(s):  
Design Space Exploration ◽  
System Level ◽  
System Level Design ◽  
Levels Of Abstraction ◽  
Technology Scaling ◽  
Communication Problems ◽  
Systems On Chip ◽  
Level Design ◽  
On Chip ◽  
Manufacturing Yield

Technology scaling into subnanometer range will have impact on the manufacturing yield and quality. At the same time, complexity and communication requirements of systems-on-chip (SoC) are increasing, thus making a SoC designer goal to design a fault-free system a very difficult task. Network-on-chip (NoC) has been proposed as one of the alternatives to solve some of the on-chip communication problems and to address dependability at various levels of abstraction. This chapter concentrates on system-level design issues of NoC-based systems. It describes various methods proposed for NoC architecture analysis and optimization, and gives an overview of different system-level fault tolerance methods. Finally, the chapter presents a system-level design framework for performing design space exploration for dependable NoC-based systems.

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