An FPGA-Based Embedded Robust Speech Recognition System Designed by Combining Empirical Mode Decomposition and a Genetic Algorithm

2012 ◽  
Vol 61 (9) ◽  
pp. 2560-2572 ◽  
Author(s):  
Shing-Tai Pan ◽  
Xu-Yu Li
Keyword(s):  
Genetic Algorithm ◽  
Speech Recognition ◽  
Empirical Mode Decomposition ◽  
Recognition System ◽  
Robust Speech Recognition ◽  
Speech Recognition System ◽  
Mode Decomposition

scholarly journals Efficient robust speech recognition with empirical mode decomposition using an FPGA chip with dual core

2020 ◽  
Vol 9 (2) ◽  
pp. 109
Author(s):  
Shing-Tai Pan ◽  
Ching-Fa Chen ◽  
Wen-Sin Tseng
Keyword(s):  
Speech Recognition ◽  
Embedded System ◽  
Empirical Mode Decomposition ◽  
Recognition System ◽  
Robust Speech Recognition ◽  
Intrinsic Mode Functions ◽  
Mode Decomposition ◽  
Original Speech ◽  
Dual Core ◽  
Computing Speed

The purpose of this paper is to accelate the computing speed of Empirical Mode Decomposition (EMD) based on multi-core embedded systems for robust speech recognition. A reconfigurable chip, Field Programmable Gate Array (FPGA), is used for the implementation of the designed system. This paper applies EMD to discompose some noised speech signals into several Intrinsic Mode Functions (IMFs). These IMFs will be combined to recover the original speech by multiplying their corresponding weights which were trained by Genetic Algorithms (GA). After applying Empirical Mode Decomposition (EMD), we obtain a cleaner speech for recognition. Due to the complexity of the computation of the EMD, a dual-core architecture of embedded system on FPGA is proposed to accelerate the computing speed of EMD for robust speech recognition. This will enhance the efficiency of embedded speech recognition system.

A robust speech recognition system against the ego noise of a robot

2010 ◽  
Author(s):  
Gökhan Ince ◽  
Kazuhiro Nakadai ◽  
Tobias Rodemann ◽  
Hiroshi Tsujino ◽  
Jun-ichi Imura
Keyword(s):  
Speech Recognition ◽  
Recognition System ◽  
Robust Speech Recognition ◽  
Speech Recognition System

VLSI Architecture for Robust Speech Recognition Systems and its Implementation on a Verification Platform

2005 ◽  
Vol 17 (4) ◽  
pp. 447-455 ◽  
Author(s):  
Shingo Yoshizawa ◽  
◽  
Noboru Hayasaka ◽  
Naoya Wada ◽  
Yoshikazu Miyanaga
Keyword(s):  
Speech Recognition ◽  
High Speed ◽  
Vlsi Architecture ◽  
Cmos Technology ◽  
Recognition System ◽  
Robust Speech Recognition ◽  
Speech Recognition System ◽  
Circuit Performance ◽  
Field Programmable ◽  
Testing Environments

This paper presents a VLSI architecture for a robust speech recognition system that enables high-speed, low-power operation. The proposed architecture improves recognition accuracy in noisy environments and realizes short-time response by implementing parallel and pipeline processing. We demonstrate improved processing time and power consumption by evaluating circuit performance in 0.25-μm CMOS technology. We also detail a verification platform that helps users implement our hardware-based robust speech recognition system. The verification platform facilitates software conversion to hardware and promptly provides testing environments on field-programmable gate arrays.

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