Design Methodology for a Robust and Energy-Efficient Millimeter-Wave Wireless Network-on-Chip

2015 ◽  
Vol 1 (1) ◽  
pp. 33-45 ◽  
Author(s):  
Naseef Mansoor ◽  
Pratheep Joe Sullivai Iruthayaraj ◽  
Amlan Ganguly
Keyword(s):  
Wireless Network ◽  
Millimeter Wave ◽  
Energy Efficient ◽  
Design Methodology ◽  
Network On Chip ◽  
On Chip

Energy efficient modulation for a wireless network-on-chip architecture

2012 ◽  
Author(s):  
Dominic DiTomaso ◽  
Soumyasanta Laha ◽  
Savas Kaya ◽  
David Matolak ◽  
Avinash Kodi
Keyword(s):  
Wireless Network ◽  
Energy Efficient ◽  
Network On Chip ◽  
On Chip

An energy-efficient partition-based XYZ-planar routing algorithm for a wireless network-on-chip

2018 ◽  
Vol 75 (2) ◽  
pp. 837-861 ◽  
Author(s):  
Fahimeh Yazdanpanah ◽  
Raheel AfsharMazayejani ◽  
Mohammad Alaei ◽  
Amin Rezaei ◽  
Masoud Daneshtalab
Keyword(s):  
Wireless Network ◽  
Energy Efficient ◽  
Routing Algorithm ◽  
Network On Chip ◽  
On Chip

scholarly journals Millimeter wave wireless network on chip using deep reinforcement learning

2020 ◽  
Author(s):  
Suraj Jog ◽  
Zikun Liu ◽  
Antonio Franques ◽  
Vimuth Fernando ◽  
Haitham Hassanieh ◽  
...  
Keyword(s):  
Reinforcement Learning ◽  
Wireless Network ◽  
Millimeter Wave ◽  
Network On Chip ◽  
On Chip

Optimization Trends for Wireless Network On-Chip

2021 ◽  
Vol 10 (1) ◽  
pp. 1-31
Author(s):  
Saliha Lakhdari ◽  
Fateh Boutekkouk
Keyword(s):  
Combinatorial Optimization ◽  
Wireless Network ◽  
Energy Efficient ◽  
High Performance ◽  
Network On Chip ◽  
Optimal Configuration ◽  
Special Focus ◽  
Minimal Cost ◽  
Wireless Interfaces ◽  
On Chip

Designing sustainable and high-performance wireless multi-core chips requires a matchless tradeoff between many aspects including scalable and reliable architectures implementation which in its turn implies aware-wideband energy-efficient wireless interfaces and adopting innovative straightforward optimization approaches to achieve the optimal configuration with a minimal cost. This paper focuses on investigating various existing designs and methodologies for wireless network on chip (WiNoC) architectures, as well as the different emerging technologies and optimization tools for the design of a robust and reliable WiNoC infrastructure with a special focus on combinatorial optimization meta-heuristics.

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