2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)
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9781479915859, 9781479915835

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DaemonGuard: O/S-assisted selective software-based Self-Testing for multi-core systems

2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) ◽

10.1109/dft.2013.6653581 ◽

2013 ◽

Cited By ~ 11

Author(s):

Michael A. Skitsas ◽

Chrysostomos A. Nicopoulos ◽

Maria K. Michael

Keyword(s):

Self Testing

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Modeling and analysis of repair and maintenance processes in Fault Tolerant Systems

2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) ◽

10.1109/dft.2013.6653616 ◽

2013 ◽

Cited By ~ 1

Author(s):

J.-Y. Hung ◽

N.-J. Park ◽

K.M. George ◽

N. Park

Keyword(s):

Fault Tolerant ◽

Modeling And Analysis ◽

Fault Tolerant Systems

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Analysing degradation effects in charge-redistribution SAR ADCs

2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) ◽

10.1109/dft.2013.6653584 ◽

2013 ◽

Cited By ~ 2

Author(s):

Muhammad Aamir Khan ◽

Hans G. Kerkhoff

Keyword(s):

Charge Redistribution

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On the correlation between Static Noise Margin and Soft Error Rate evaluated for a 40nm SRAM cell

2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) ◽

10.1109/dft.2013.6653597 ◽

2013 ◽

Cited By ~ 3

Author(s):

Elena I. Vatajelu ◽

G. Tsiligiannis ◽

L. Dilillo ◽

A. Bosio ◽

P. Girard ◽

...

Keyword(s):

Error Rate ◽

Soft Error ◽

Static Noise Margin ◽

Soft Error Rate ◽

Noise Margin ◽

Sram Cell ◽

Static Noise

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Reliability analysis of combinational circuits with the influences of noise and single-event transients

2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) ◽

10.1109/dft.2013.6653609 ◽

2013 ◽

Author(s):

Kaikai Liu ◽

Hao Cai ◽

Ting An ◽

Lirida Naviner ◽

Jean-Francois Naviner ◽

...

Keyword(s):

Reliability Analysis ◽

Combinational Circuits ◽

Single Event ◽

Single Event Transients

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Technology-aware system failure analysis in the presence of soft errors by Mixture Importance Sampling

2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) ◽

10.1109/dft.2013.6653593 ◽

2013 ◽

Cited By ~ 8

Author(s):

Veit B. Kleeberger ◽

Daniel Mueller-Gritschneder ◽

Ulf Schlichtmann

Keyword(s):

Failure Analysis ◽

Importance Sampling ◽

Soft Errors ◽

System Failure

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F-DICE: A multiple node upset tolerant flip-flop for highly radioactive environments

2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) ◽

10.1109/dft.2013.6653591 ◽

2013 ◽

Cited By ~ 7

Author(s):

Stefano Campitelli ◽

Marco Ottavi ◽

Salvatore Pontarelli ◽

Alessandro Marchioro ◽

Daniele Felici ◽

...

Keyword(s):

Flip Flop ◽

Multiple Node

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A low cost reliable architecture for S-Boxes in AES processors

2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) ◽

10.1109/dft.2013.6653599 ◽

2013 ◽

Cited By ~ 1

Author(s):

Ting An ◽

Lirida Alves de Barros Naviner ◽

Philippe Matherat

Keyword(s):

Low Cost

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Implementing triple adjacent Error Correction in double error correction Orthogonal Latin Squares Codes

2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) ◽

10.1109/dft.2013.6653601 ◽

2013 ◽

Cited By ~ 7

Author(s):

P. Reviriego ◽

S. Liu ◽

J.A. Maestro ◽

S. Lee ◽

N.A Touba ◽

...

Keyword(s):

Error Correction ◽

Latin Squares ◽

Orthogonal Latin Squares

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Reconfigurable distributed fault tolerant routing algorithm for on-chip networks

2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) ◽

10.1109/dft.2013.6653621 ◽

2013 ◽

Cited By ~ 3

Author(s):

Manoj Kumar ◽

Pankaj ◽

Vijay Laxmi ◽

Manoj Singh Gaur ◽

Seok-Bum Ko

Keyword(s):

Fault Tolerant ◽

Routing Algorithm ◽

On Chip

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2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

DaemonGuard: O/S-assisted selective software-based Self-Testing for multi-core systems

Modeling and analysis of repair and maintenance processes in Fault Tolerant Systems

Analysing degradation effects in charge-redistribution SAR ADCs

On the correlation between Static Noise Margin and Soft Error Rate evaluated for a 40nm SRAM cell

Reliability analysis of combinational circuits with the influences of noise and single-event transients

Technology-aware system failure analysis in the presence of soft errors by Mixture Importance Sampling

F-DICE: A multiple node upset tolerant flip-flop for highly radioactive environments

A low cost reliable architecture for S-Boxes in AES processors

Implementing triple adjacent Error Correction in double error correction Orthogonal Latin Squares Codes

Reconfigurable distributed fault tolerant routing algorithm for on-chip networks

2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)
Latest Publications