Analysis and Design of a Chip Filter With Low Insertion Loss and Two Adjustable Transmission Zeros Using 0.18-$\mu{\hbox{m}}$ CMOS Technology

2010 ◽  
Vol 58 (1) ◽  
pp. 176-184 ◽  
Author(s):  
Chin-Lung Yang ◽  
Shin-Yi Shu ◽  
Yi-Chyun Chiang
Frequenz ◽  
2016 ◽  
Vol 70 (9-10) ◽  
Author(s):  
Chuanming Zhu ◽  
Jin Xu ◽  
Wei Kang ◽  
Zhenxin Hu ◽  
Wen Wu

AbstractIn this paper, a miniaturized dual-band bandpass filter (DB-BPF) using embedded dual-mode resonator (DMR) with controllable bandwidths is proposed. Two passbands are generated by two sets of resonators operating at two different frequencies. One set of resonators is utilized not only as the resonant elements that yield the lower passband, but also as the feeding structures with source-load coupling to excite the other to produce the upper passband. Sufficient degrees of freedom are achieved to control the center frequencies and bandwidths of two passbands. Moreover, multiple transmission zeros (TZs) are created to improve the passband selectivity of the filter. The design of the filter has been demonstrated by the measurement. The filter features not only miniaturized circuit sizes, low insertion loss, independently controllable central frequencies, but also controllable bandwidths and TZs.


2012 ◽  
Vol 487 ◽  
pp. 125-129
Author(s):  
Kai Yu Zhao ◽  
Lin Li

A compact lowpass filter using two single-sided compact microstrip resonator cells (CMRCs)with low insertion loss and broad bandwidth is presented. The cutoff frequency is about 1.4 GHz, the insertion loss is less than 0.6 dB and the 20dB bandwidth is up to the range from 2.1 GHz to 9.8 GHz by means of introducing four transmission zeros through two CMRCs. In addition, the simulated results demonstrate that the proposed filter is characterized by a compact size, low insertion loss, sharp transition, low return loss and wide bandwidth.


Micromachines ◽  
2015 ◽  
Vol 6 (3) ◽  
pp. 390-395 ◽  
Author(s):  
Xiao-Dong Deng ◽  
Yihu Li ◽  
Wen Wu ◽  
Yong-Zhong Xiong

2013 ◽  
Vol 49 (7) ◽  
pp. 477-479 ◽  
Author(s):  
Fu‐Chang Chen ◽  
Jie‐Ming Qiu ◽  
Zhi‐Han Chen ◽  
Qing‐Xin Chu

2011 ◽  
Vol 110-116 ◽  
pp. 5500-5504
Author(s):  
Ki Jin Kim ◽  
Tae Ho Lim ◽  
S.H. Park ◽  
K. H. Ahn

This paper proposes a high efficiency power amplifier with a diode linearizer and voltage combining transformers in a standard 0.13-μm TSMC CMOS technology. The 3-D simulated transformer adopts multi-finger architecture which provides low insertion loss and allows high current capacity on the transformer. With the 4 differentially cascaded connected multi-finger transformers, the amplifier delivers more than 1W output power under 1.8 V supply condition. To enhance linearity of the power amplifier, the diode configuration bias circuit is used in this paper. With all integration of transformers, balun, diode bias circuits and same 4 diff-amps, the prototype Class AB Power Amplifier shows 32dBm saturation power at 2.4 GHz. Due to the diode linearizer the output P1dB is 30.8 dBm with 28 % Power Added Efficiency.


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