Broadband Performance Assessment of an RF Power Transistor Employing the Real Frequency Technique

selected active device is essential to design an RF power amplifier for optimum gain and power added efficiency. As they are obtained, these impedances may not be realizable network functions over the desired frequency band to yield the input and the output matching networks for the amplifier. Therefore, in this paper, first, we introduce a new method to test if a given impedance is realizable. Then, a novel “Real Frequency Line Segment Technique” based numerical procedure is introduced to assess the gain-bandwidth limitations of the given source and load impedances, which in turn results in the ultimate RF-power intake/ delivering performance of the amplifier. During the numerical performance assessments process, a robust tool called “Virtual Gain Optimization” is presented. Finally, a new definition called “Power-Performance-Product” is introduced to measure the quality of an active device. Examples are presented to test the realizability of the given source/load pull data and to assess the gain-bandwidth limitations of the given source/load pull impedances for a 45W-GaN power transistor, namely “Cree CG2H40045”, over 0.8 -3.8 GHz bandwidth.

Broadband Performance Assessment of an RF Power Transistor Employing the Real Frequency Technique

selected active device is essential to design an RF power amplifier for optimum gain and power added efficiency. As they are obtained, these impedances may not be realizable network functions over the desired frequency band to yield the input and the output matching networks for the amplifier. Therefore, in this paper, first, we introduce a new method to test if a given impedance is realizable. Then, a novel “Real Frequency Line Segment Technique” based numerical procedure is introduced to assess the gain-bandwidth limitations of the given source and load impedances, which in turn results in the ultimate RF-power intake/ delivering performance of the amplifier. During the numerical performance assessments process, a robust tool called “Virtual Gain Optimization” is presented. Finally, a new definition called “Power-Performance-Product” is introduced to measure the quality of an active device. Examples are presented to test the realizability of the given source/load pull data and to assess the gain-bandwidth limitations of the given source/load pull impedances for a 45W-GaN power transistor, namely “Cree CG2H40045”, over 0.8 -3.8 GHz bandwidth.

A Wide-Band High-Gain Doherty Power Amplifier With Class-AB HEMT Amplifiers

In this paper, an attempt has been made to design a Doherty power amplifier (DPA) with high-gain and wide-band. For this purpose, two peak amplifiers are used to improve the performance of the main amplifier. Main and auxiliary amplifiers with the same structure to the class-AB type and by using micro-strip lines in place of input/output and load matching networks, transmission lines and inductors of drain and gate, that minimize the losses in the DPA. The current DPA is implemented with GaN_HEMT_CLF1G0530_100v transistor and Rogers4003 substrate, which for 1GHz frequency in 0.5-1.5GHz bandwidth will be able to be at P-1dB point (this point, input power as 30dBm and output power as 47.98dBm) increase Drain efficiency and Power added efficiency (PAE) to 81.95% and 80.73%, respectively. The DPA helps to expand the back-off region and extend the linearity region, so the Peak to average power ratio (PAPR) will be 5.21dB and the Adjacent channel power ratio (ACPR) as 58.7dBc. A gain of 17.06-17.92dB was also obtained, which is significant compared to the results of similar samples.

AlN/GaN MISHEMTs on Si with in-situ SiN as gate dielectric for power amplifiers in mobile SoCs

AlN/GaN metal-insulator-semiconductor high electron mobility transistors (MISHEMTs) on silicon substrate using in-situ SiN as gate dielectric were fabricated and their RF power performance at mobile system-on-chip (SoC) compatible voltages was measured. At a mobile SoC-compatible supply voltage of Vd = 3.5 V/5 V, the 90-nm gate-length AlN/GaN MISHEMTs showed a maximum power-added efficiency (PAE) of 62%/58%, a maximum output power density (Poutmax) of 0.44 W/mm/0.84 W/mm and a linear gain of 20 dB/19 dB at the frequency of 5 GHz. These results suggest that the in-situ-SiN/AlN/GaN-on-Si MISHEMTs are promising for RF power amplifiers in 5G mobile SoC applications.

Optimization Technique for High-Gain CMOS Power Amplifier for 5G Applications

In this study, a differential power amplifier (PA) with a high gain of over 30 dB by configuring a three-stage common source unit amplifier was designed. To ensure the stability of the high-gain differential PA, the analysis to apply the capacitive neutralization method to the differential common source PA was conducted. From the analysis, the required neutralized capacitance was quantitatively calculated from the estimated parasitic components of a power cell used in the PA. To verify the feasibility of the proposed optimization technique, a Ka-band PA was designed with a 65 nm RFCMOS process. The measurement results showed a gain of 30.7 dB. The saturated output power was measured as 16.1 dBm, maximum power-added efficiency (PAE) was 29.7%, and P1dB was 13.1 dBm.

Fabrication and characterization of AlGaN/GaN HEMTs with high power gain and efficiency at 8 GHz

State-of-the-art AlGaN/GaN high electron mobility structures were grown on semi-insulating 4H-SiC substrates by MOCVD and X-band microwave power high electron mobility transistors were fabricated and characterized. Hall mobility of 2291.1 cm2/(V·s) and two-dimensional electron gas density of 9.954 × 1012 cm–2 were achieved at 300 K. The HEMT devices with a 0.45-μm gate length exhibited maximum drain current density as high as 1039.6 mA/mm and peak extrinsic transconductance of 229.7 mS/mm. The f T of 30.89 GHz and f max of 38.71 GHz were measured on the device. Load-pull measurements were performed and analyzed under (–3.5, 28) V, (–3.5, 34) V and (–3.5, 40) V gate/drain direct current bias in class-AB, respectively. The uncooled device showed high linear power gain of 17.04 dB and high power-added efficiency of 50.56% at 8 GHz when drain biased at (–3.5, 28) V. In addition, when drain biased at (–3.5, 40) V, the device exhibited a saturation output power density up to 6.21 W/mm at 8 GHz, with a power gain of 11.94 dB and a power-added efficiency of 39.56%. Furthermore, the low f max/f T ratio and the variation of the power sweep of the device at 8 GHz with drain bias voltage were analyzed.

Frequency analysis of load modulation networks for asymmetric Doherty power amplifiers in GaN

This paper investigates the frequency response of load modulation networks for asymmetric Doherty power amplifiers (ADPA) with an output back-off power level larger than 6 dB and a power ratio of peak to main amplifier (N − 1) larger than 1. The influence of the main path impedance transformer (IT) on the Doherty impedances at main and peak path as well as on the ADPA's efficiency is analyzed. Scaling of the main IT's characteristic impedance via ξ indicates a maximum broadband matching for an input voltage Vin of ξ · Vin,max. By weighting the frequency- and ξ-dependent efficiency curves using a probability density function (PDF), an optimum is obtained for ξ = 1/N. To verify the theory, three ADPAs with different ξ-scaled ITs are designed, measured, and compared. For the design at 3.6 GHz, a gallium nitride (GaN) transistor is used. By means of the intrinsic node matching technique, matching at the current source plane is obtained. In laboratory measurements, the ADPA with ξ = 1/N achieves a power-added efficiency (PAE) of 63% at 42 dBm output power and a PDF-weighted average PAE of 38.8% within 400 MHz bandwidth for 8 dB peak-to-average power ratio. Comparison with similar state-of-the-art ADPAs in GaN technology shows highest PAE and operation power gain GP for center frequencies larger than 3.0 GHz.

Design and Optimization of 2.1 mW ULP Doherty Power Amplifier with Interstage Capacitances Using 65 nm CMOS Technology

This research proposed the design and calculations of ultra-low power (ULP) Doherty power amplifier (PA) using 65 nm CMOS technology. Both the main and the peaking amplifiers are designed and optimized using equivalent lumped parameters and power combiner models. The operation has been performed in RF-nMOS subthreshold or triode region to achieve ultra-low power (ULP) and to improve the linearity of the overall power amplifier (PA). The novel design consumes a DC power of 2.1 mW, power-added efficiency (PAE) of 29.8%, operating at 2.4 GHz band, and output referred 1 dB compression point at 4.1dBm. The simulation results show a very good capability of drive current, high gain, and very low input and output insertion losses.

Adoption of the Wet Surface Treatment Technique for the Improvement of Device Performance of Enhancement-Mode AlGaN/GaN MOSHEMTs for Millimeter-Wave Applications

In this work, a low-power plasma oxidation surface treatment followed by Al2O3 gate dielectric deposition technique is adopted to improve device performance of the enhancement-mode (E-mode) AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOSHEMTs) intended for applications at millimeter-wave frequencies. The fabricated device exhibited a threshold voltage (Vth) of 0.13 V and a maximum transconductance (gm) of 484 (mS/mm). At 38 GHz, an output power density of 3.22 W/mm with a power-added efficiency (PAE) of 34.83% were achieved. Such superior performance was mainly attributed to the high-quality Al2O3 layer with a smooth surface which also suppressed the current collapse phenomenon.