Speed-up of acoustic simulation techniques for 2D sparse array optimization by simulated annealing

2015 ◽  
Author(s):  
Emmanuel Roux ◽  
Alessandro Ramalli ◽  
Piero Tortoli ◽  
Christian Cachard ◽  
Marc Robini ◽  
...  
Keyword(s):  
Simulated Annealing ◽  
Sparse Array ◽  
Acoustic Simulation ◽  
Simulation Techniques ◽  
Speed Up ◽  
Array Optimization

Sparse Array Optimization Using Simulated Annealing and Compressed Sensing for Near-Field Millimeter Wave Imaging

2014 ◽  
Vol 62 (4) ◽  
pp. 1716-1722 ◽  
Author(s):  
Borja Gonzalez-Valdes ◽  
Gregory Allan ◽  
Yolanda Rodriguez-Vaqueiro ◽  
Yuri Alvarez ◽  
Spiros Mantzavinos ◽  
...  
Keyword(s):  
Simulated Annealing ◽  
Compressed Sensing ◽  
Millimeter Wave ◽  
Near Field ◽  
Millimeter Wave Imaging ◽  
Sparse Array ◽  
Wave Imaging ◽  
Array Optimization

scholarly journals Hybrid Genetic Algorithm and Simulated Annealing for Function Optimization

2017 ◽  
Vol 1 (2) ◽  
pp. 82 ◽  
Author(s):  
Tirana Noor Fatyanosa ◽  
Andreas Nugroho Sihananto ◽  
Gusti Ahmad Fanshuri Alfarisy ◽  
M Shochibul Burhan ◽  
Wayan Firdaus Mahmudy
Keyword(s):  
Genetic Algorithm ◽  
Simulated Annealing ◽  
Optimization Problems ◽  
Linear Optimization ◽  
Hybrid Genetic Algorithm ◽  
Optimal Solution ◽  
Function Optimization ◽  
Non Linear ◽  
Speed Up ◽  
Linear Problems

The optimization problems on real-world usually have non-linear characteristics. Solving non-linear problems is time-consuming, thus heuristic approaches usually are being used to speed up the solution’s searching. Among of the heuristic-based algorithms, Genetic Algorithm (GA) and Simulated Annealing (SA) are two among most popular. The GA is powerful to get a nearly optimal solution on the broad searching area while SA is useful to looking for a solution in the narrow searching area. This study is comparing performance between GA, SA, and three types of Hybrid GA-SA to solve some non-linear optimization cases. The study shows that Hybrid GA-SA can enhance GA and SA to provide a better result

scholarly journals HotSpot Thermal Floorplan Solver Using Conjugate Gradient to Speed Up

2018 ◽  
Vol 2018 ◽  
pp. 1-8 ◽  
Author(s):  
Zhonghua Jiang ◽  
Ning Xu
Keyword(s):  
Simulated Annealing ◽  
Conjugate Gradient ◽  
Decomposition Method ◽  
Sparse Matrix ◽  
Lu Decomposition ◽  
Ratio Curve ◽  
Resistance Model ◽  
Speed Up ◽  
Iterative Framework ◽  
Conjugate Gradient Solver

We proposed to use the conjugate gradient method to effectively solve the thermal resistance model in HotSpot thermal floorplan tool. The iterative conjugate gradient solver is suitable for traditional sparse matrix linear systems. We also defined the relative sparse matrix in the iterative thermal floorplan of Simulated Annealing framework algorithm, and the iterative method of relative sparse matrix could be applied to other iterative framework algorithms. The experimental results show that the running time of our incremental iterative conjugate gradient solver is speeded up approximately 11x compared with the LU decomposition method for case ami49, and the experiment ratio curve shows that our iterative conjugate gradient solver accelerated more with increasing number of modules.

Spiral array inspired multi-depth cost function for 2D sparse array optimization

2015 ◽  
Author(s):  
Emmanuel Roux ◽  
Alessandro Ramalli ◽  
Marc Robini ◽  
Herve Liebgott ◽  
Christian Cachard ◽  
...  
Keyword(s):  
Cost Function ◽  
Sparse Array ◽  
Array Optimization ◽  
Spiral Array

scholarly journals Two-dimensional Placement Using Tabu Search

VLSI Design ◽  
2001 ◽  
Vol 12 (1) ◽  
pp. 13-23
Author(s):  
John M. Emmert ◽  
Dinesh K. Bhatia
Keyword(s):  
Simulated Annealing ◽  
Tabu Search ◽  
Optimization Technique ◽  
Vlsi Design ◽  
Two Dimensional ◽  
Search Technique ◽  
Quality Of Results ◽  
Circuit Performance ◽  
Speed Up

Search based placement of modules is an important problem in VLSI design. It is always desired that the search should converge quickly to a high quality solution. This paper presents a tabu search based optimization technique to place modules on a regular two-dimensional array. The goal of the technique is to speed up the placement process. The technique is based on a two-step placement strategy. The first step is targeted toward improving circuit routability and the second step addresses circuit performance. The technique is demonstrated through placement of several benchmark circuits on academic as well as commercial FPGAs. Results are compared to placements generated by commercial CAE tools and published simulated annealing based techniques. The tabu search technique compares favorably to published simulated annealing based techniques, and it demonstrates an average execution time speedup of 20 with no impact on quality of results when compared to commercial tools.

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