Enabling fast Network-on-Chip topology selection: an FPGA-based runtime reconfigurable prototyper

2010 ◽  
Author(s):  
Paolo Meloni ◽  
Simone Secchi ◽  
Luigi Raffo
Keyword(s):  
Network On Chip ◽  
Fast Network ◽  
On Chip ◽  
Topology Selection

scholarly journals A Network Traffic Generator Model for Fast Network-on-Chip Simulation

2005 ◽  
Author(s):  
S. Mahadevan ◽  
F. Angiolini ◽  
M. Storgaard ◽  
R.G. Olsen ◽  
J. Sparso ◽  
...  
Keyword(s):  
Network Traffic ◽  
Network On Chip ◽  
Generator Model ◽  
Traffic Generator ◽  
Fast Network ◽  
On Chip

scholarly journals A Network Traffic Generator Model for Fast Network-on-Chip Simulation

2008 ◽  
pp. 173-184 ◽  
Author(s):  
Shankar Mahadevan ◽  
Federico Angiolini ◽  
Jens Sparsø ◽  
Michael Storgaard ◽  
Jan Madsen ◽  
...  
Keyword(s):  
Network Traffic ◽  
Network On Chip ◽  
Generator Model ◽  
Traffic Generator ◽  
Fast Network ◽  
On Chip

A Fast Network-on-Chip Simulator with QEMU and SystemC

2012 ◽  
Author(s):  
Keita Nakajima ◽  
Takuji Hieda ◽  
Ittetsu Taniguchi ◽  
Hiroyuki Tomiyama ◽  
Hiroaki Takada
Keyword(s):  
Network On Chip ◽  
Fast Network ◽  
On Chip

Fast Network-on-Chip Design

2013 ◽  
pp. 67-127
Author(s):  
Ayan Mandal ◽  
Sunil P. Khatri ◽  
Rabi N. Mahapatra
Keyword(s):  
Network On Chip ◽  
Chip Design ◽  
Fast Network ◽  
On Chip

Pre-allocated Path Based Low Latency Router Architecture for Network-on-chip

2014 ◽  
Vol 35 (2) ◽  
pp. 341-346
Author(s):  
Xiao-fu Zheng ◽  
Hua-xi Gu ◽  
Yin-tang Yang ◽  
Zhong-fan Huang
Keyword(s):  
Network On Chip ◽  
Low Latency ◽  
Router Architecture ◽  
On Chip
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