Effect of jitter-reducing encoders on CAN error detection mechanisms

Author(s):  
Gianluca Cena ◽  
Ivan Cibrario Bertolotti ◽  
Tingting Hu ◽  
Adriano Valenzano
1990 ◽  
Vol 30 (1-5) ◽  
pp. 513-520 ◽  
Author(s):  
Henrique Madeira ◽  
Gonçalo Quadros ◽  
João Gabriel Silva

1991 ◽  
Vol 32 (1-5) ◽  
pp. 253-259 ◽  
Author(s):  
Andreas Steininger ◽  
Herbert Schweinzer

2010 ◽  
Vol 26 (3) ◽  
pp. 323-335 ◽  
Author(s):  
Kiran Kumar Reddy ◽  
Bharadwaj S. Amrutur ◽  
Rubin A. Parekhji

VLSI Design ◽  
1998 ◽  
Vol 5 (4) ◽  
pp. 313-331
Author(s):  
Mark G. Karpovsky

In this paper we present an approach for combining on-line concurrent checking (CC) with off-line built-in self-test (BIST). We will show that a reduction of an aliasing probability can be obtained for manufacturing testing by monitoring the output of a concurrent checker and a reduction of a probability of not detecting an error in the computing mode can be obtained by a short periodic BIST. We will present a technique for optimal selection of error-detecting codes for combined on-line CC and off-line space-time compression of test responses for BIST and estimate probabilities of not detecting an error for the approach based on integrating CC and BIST. We also present a technique for on-line error-detection in space-time compressors of test responses for BIST.


Sign in / Sign up

Export Citation Format

Share Document