Analysis of Single Event Effects on Embedded Processor

The continuous scaling of electronic components has led to the development of high-performance microprocessors which are even suitable for safety-critical applications where radiation-induced errors, such as single event effects (SEEs), are one of the most important reliability issues. This work focuses on the development of a fault injection environment capable of analyzing the impact of errors on the functionality of an ARM Cortex-A9 microprocessor embedded within a Zynq-7000 AP-SoC, considering different fault models affecting both the system memory and register resources of the embedded processor. We developed a novel Python-based fault injection platform for the emulation of radiation-induced faults within the AP-SoC hardware resources during the execution of software applications. The fault injection approach is not intrusive, and it does not require modifying the software application under evaluation. The experimental analyses have been performed on a subset of the MiBench benchmark software suite. Fault injection results demonstrate the capability of the developed method and the possibility of evaluating various sets of fault models.

Series And Parallel Arc Fault Detection Based on Discrete Wavelet VS. FFT Techniques

Arc problems are most commonly caused by electrical difficulties such as worn cables and improper connections. Electrical fires are caused by arc faults, which generate tremendous temperatures and discharge molten metal. Every year, flames of this nature inflict a great lot of devastation and loss. A novel approach for identifying residential series and parallel arc faults is presented in this study. To begin, arc faults in series and parallel are simulated using a suitable simulation arc model. The fault characteristics are then recovered using a signal processing technique based on the fault detection technique called Discrete Wavelet Transform (DWT), which is built in MATLAB/Simulink. Then came db2, and one level was discovered for obtaining arc-fault features. The suitable mother and level of wavelet transform should be used, and try to compare results with conventional methods (FFT-Fast Fourier Transform). MATLAB was used to build and simulate arc-fault models with these techniques.

A review paper on memory fault models and test algorithms

Testing embedded memories in a chip can be very challenging due to their high-density nature and manufactured using very deep submicron (VDSM) technologies. In this review paper, functional fault models which may exist in the memory are described, in terms of their definition and detection requirement. Several memory testing algorithms that are used in memory built-in self-test (BIST) are discussed, in terms of test operation sequences, fault detection ability, and also test complexity. From the studies, it shows that tests with 22 N of complexity such as March SS and March AB are needed to detect all static unlinked or simple faults within the memory cells. The N in the algorithm complexity refers to Nx*Ny*Nz whereby Nx represents the number of rows, Ny represents the number of columns and Nz represents the number of banks. This paper also looks into optimization and further improvement that can be achieved on existing March test algorithms to increase the fault coverage or to reduce the test complexity.

FTT-NAS: Discovering Fault-tolerant Convolutional Neural Architecture

With the fast evolvement of embedded deep-learning computing systems, applications powered by deep learning are moving from the cloud to the edge. When deploying neural networks (NNs) onto the devices under complex environments, there are various types of possible faults: soft errors caused by cosmic radiation and radioactive impurities, voltage instability, aging, temperature variations, malicious attackers, and so on. Thus, the safety risk of deploying NNs is now drawing much attention. In this article, after the analysis of the possible faults in various types of NN accelerators, we formalize and implement various fault models from the algorithmic perspective. We propose Fault-Tolerant Neural Architecture Search (FT-NAS) to automatically discover convolutional neural network (CNN) architectures that are reliable to various faults in nowadays devices. Then, we incorporate fault-tolerant training (FTT) in the search process to achieve better results, which is referred to as FTT-NAS. Experiments on CIFAR-10 show that the discovered architectures outperform other manually designed baseline architectures significantly, with comparable or fewer floating-point operations (FLOPs) and parameters. Specifically, with the same fault settings, F-FTT-Net discovered under the feature fault model achieves an accuracy of 86.2% (VS. 68.1% achieved by MobileNet-V2), and W-FTT-Net discovered under the weight fault model achieves an accuracy of 69.6% (VS. 60.8% achieved by ResNet-18). By inspecting the discovered architectures, we find that the operation primitives, the weight quantization range, the capacity of the model, and the connection pattern have influences on the fault resilience capability of NN models.

Demystifying Unexpected Silicon Responses through User-Defined Fault Models (UDFM) and Failure Analysis

Failure Analysis (FA) plays an important role during silicon development and yield ramp up, helping identify critical test, design marginality and process issues in a timely and efficient manner. FA techniques typically rely on diagnosis callouts as a starting point for debug. Diagnostic algorithms rely on the error logs collected on production patterns which are generated to detect Stuck-at Faults (SAF) and Transition Delay Faults (TDF). Typically, SAF patterns screen out the static defects and TDF patterns test for transient fails. But often, we see cases where a SAF pattern shmoo is clean but the TDF pattern shmoo is a gross failure indicating a cell-internal static defect missed by the traditional SAF patterns. In this work, we will present our own developed User-Defined Fault Model, which targets cell-internal faults to explain unexpected silicon observations. An added advantage of the work can be seen in improving diagnosis results on the error logs collected using these targeted UDFM patterns. Since UDFM utilizes targeted fault excitation, the diagnosis algorithm results in better callouts. In this paper, we will also propose a custom diagnosis flow using our in-house UDFM to achieve better resolution. Three FA case studies will be presented to showcase the usefulness and effectivity of the proposed methods.

Optimal Reduction in the Number of Test Vectors for Soft Processor Cores Implemented in FPGA

Testing FPGA-based soft processor cores requires a completely different methodology in comparison to standard processors. The stuck-at fault model is insufficient, as the logic is implemented by lookup tables (LUTs) in FPGA, and this SRAM-based LUT memory is vulnerable to single-event upset (SEU) mainly caused by cosmic radiations. Consequently, in this paper, we used combined SEU-induced and stuck-at fault models to simulate every possible fault. The test program written in an assembler was based on the bijective property. Furthermore, the fault detection matrix was determined, and this matrix describes the detectability of every fault by every test vector. The major novelty of this paper is the optimal reduction in the number of required test vectors in such a way that fault coverage is not reduced. Furthermore, this paper also studied the optimal selection of test vectors when only 95% maximal fault coverage is acceptable; in such a case, only three test vectors are required. Further, local and global test vector selection is also described.

Rapid and Quantitative Uncertainty Estimation of Coseismic Slip Distribution for Large Interplate Earthquakes Using Real-time GNSS Data and Its Application to Tsunami Inundation Prediction

This study proposes a new method for the uncertainty estimation of coseismic slip distribution on the plate interface deduced from real-time global navigation satellite system (GNSS) data and explores its application for tsunami inundation prediction. Jointly developed by the Geospatial Information Authority of Japan and Tohoku University, REGARD (REal-time GEONET Analysis system for Rapid Deformation monitoring) estimates coseismic fault models (a single rectangular fault model and slip distribution model) in real time to support tsunami prediction. The estimated results are adopted as part of the Disaster Information System, which is used by the Cabinet Office of the Government of Japan to assess tsunami inundation and damage. However, the REGARD system currently struggles to estimate the quantitative uncertainty of the estimated result, although the obtained result should contain both observation and modeling errors caused by the model settings. Understanding such quantitative uncertainties based on the input data is essential for utilizing this resource for disaster response. We developed an algorithm that estimates the coseismic slip distribution and its uncertainties using Markov chain Monte Carlo methods. We focused on the Nankai Trough of southwest Japan, where megathrust earthquakes have repeatedly occurred, and used simulation data to assume a Hoei-type earthquake. We divided the 2951 rectangular subfaults on the plate interface and designed a multistage sampling flow with stepwise perturbation groups. As a result, we successfully estimated the slip distribution and its uncertainty at the 95% confidence interval of the posterior probability density function. Furthermore, we developed a new visualization procedure that shows the risk of tsunami inundation and the probability on a map. Under the algorithm, we regarded the Markov chain Monte Carlo samples as individual fault models and clustered them using the k-means approach to obtain different tsunami source scenarios. We then calculated the parallel tsunami inundations and integrated the results on the map. This map, which expresses the uncertainties of tsunami inundation caused by uncertainties in the coseismic fault estimation, offers quantitative and real time insights into possible worst-case scenarios.

Modeling and Numerical Simulation of a Buoyancy Controlled Ocean Current Turbine

Increased global renewable power demands and the high energy density of ocean currents have motivated the development of ocean current turbines (OCTs). These compliantly mooring systems will maintain desired near-surface operating depths using variable buoyancy, lifting surface, sub-sea winches, and/or surface buoys. This paper presents a complete numerical simulation of a 700 kW variable buoyancy controlled OCT that includes detailed turbine system, inflow, actuator (i.e., generator and variable buoyancy), sensor, and fault models. Simulation predictions of OCT performance are made for normal, hurricane, and fault scenarios. Results suggest this OCT can operate between depths of 38 m to 329 m for all homogeneous flow speeds between 1.0-2.5 m/s. Fault scenarios show that rotor braking results in a rapid vertical OCT system assent and that blade pitch faults create power fluctuations apparent in the frequency domain. Finally, simulated OCT operations in measured ocean currents (i.e., normal and hurricane conditions) quantify power statistics and system behavior typical and extreme conditions.