A Switchable Chaotic Oscillator with Two Amplitude–Frequency Controllers

2017 ◽  
Vol 26 (10) ◽  
pp. 1750158 ◽  
Author(s):  
Wen Hu ◽  
Akif Akgul ◽  
Chunbiao Li ◽  
Taicheng Zheng ◽  
Peng Li
Keyword(s):  
Chaotic System ◽  
Value Function ◽  
Chaotic Signal ◽  
Signal Generator ◽  
Chaotic Oscillator ◽  
Absolute Value ◽  
Independent Amplitude ◽  
Chaotic Signals ◽  
Chaotic Signal Generator ◽  
Frequency Controller

A simple chaotic system with a single nonquadratic term is developed to be a switchable chaotic signal generator in this paper. Additional nonlinearity of the absolute value function is introduced for reforming the structure without damaging the basic dynamics but yielding a new independent amplitude–frequency controller. A switchable chaotic experimental oscillator is designed afterwards, where two coefficients corresponding to two independent rheostats rescale the amplitude and frequency of the chaotic signals smoothly. To our knowledge, this has never been found in other chaotic oscillators.

GENERALIZED SYNCHRONIZATION IN DOUBLY DRIVEN CHAOTIC SYSTEM

2006 ◽  
Vol 20 (24) ◽  
pp. 3477-3485
Author(s):  
XIA HUANG ◽  
JIAN GAO ◽  
DAIHAI HE ◽  
ZHIGANG ZHENG
Keyword(s):  
Chaotic System ◽  
Conditional Entropy ◽  
Chaotic Oscillator ◽  
Generalized Synchronization ◽  
Entropy Analysis ◽  
Entropy Spectrum ◽  
Chaotic Signals ◽  
Coupling Strengths ◽  
Conventional Methods ◽  
Parameter Values

Generalized synchronization (GS) of a chaotic oscillator driven by two chaotic signals is investigated in this paper. Both receiver and drivers are the same kind of oscillators with mismatched parameter values. Partial and global GS may appear depending on coupling strengths. An approach based on the conditional entropy analysis is presented to test the partial GS, which is difficult to determine with conventional methods. A trough in conditional entropy spectrum indicates partial GS between the receiver and one of the drivers.

Estimation of Chaotic Signals Based on Symbolic Distance and Its Application

2003 ◽  
Vol 17 (22n24) ◽  
pp. 4227-4231
Author(s):  
Wenguang Jin ◽  
Yicheng Zeng
Keyword(s):  
Chaotic System ◽  
Efficient Method ◽  
Chaotic Signal ◽  
Initial Condition ◽  
Weak Signal ◽  
Signal Estimation ◽  
Symbolic Sequence ◽  
System A ◽  
Chaotic Signals ◽  
Symbolic Distance

An efficient method for chaotic signal estimation is described based on the connection between the symbolic sequence and the initial condition of a chaotic system. A distance between the orbits has been defined. The method can be used in weak signal measuring. Circuit experiment results show that the precision is more than 0.05/100.

Design and FPGA Implementation of a Universal Chaotic Signal Generator Based on the Verilog HDL Fixed-Point Algorithm and State Machine Control

2017 ◽  
Vol 27 (03) ◽  
pp. 1750040 ◽  
Author(s):  
Mo Qiu ◽  
Simin Yu ◽  
Yuqiong Wen ◽  
Jinhu Lü ◽  
Jianbin He ◽  
...  
Keyword(s):  
Fixed Point ◽  
Chaotic Signal ◽  
State Machine ◽  
Signal Generator ◽  
Iterative Sequence ◽  
Basic Operation ◽  
Verilog Hdl ◽  
Fixed Point Algorithm ◽  
Machine Control ◽  
Chaotic Signal Generator

In this paper, a novel design methodology and its FPGA hardware implementation for a universal chaotic signal generator is proposed via the Verilog HDL fixed-point algorithm and state machine control. According to continuous-time or discrete-time chaotic equations, a Verilog HDL fixed-point algorithm and its corresponding digital system are first designed. In the FPGA hardware platform, each operation step of Verilog HDL fixed-point algorithm is then controlled by a state machine. The generality of this method is that, for any given chaotic equation, it can be decomposed into four basic operation procedures, i.e. nonlinear function calculation, iterative sequence operation, iterative values right shifting and ceiling, and chaotic iterative sequences output, each of which corresponds to only a state via state machine control. Compared with the Verilog HDL floating-point algorithm, the Verilog HDL fixed-point algorithm can save the FPGA hardware resources and improve the operation efficiency. FPGA-based hardware experimental results validate the feasibility and reliability of the proposed approach.

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