Approximate Compressor-Based Multiplier Design Methodology for Error-Resilient Digital Signal Processing

2020 ◽  
Vol 29 (14) ◽  
pp. 2050233
Author(s):  
Zhixi Yang ◽  
Xianbin Li ◽  
Jun Yang
Keyword(s):  
Image Processing ◽  
Signal Processing ◽  
Digital Signal Processing ◽  
Resource Utilization ◽  
Finite Impulse Response ◽  
Digital Signal ◽  
Fir Filter ◽  
Electrical Performance ◽  
Approximate Computing ◽  
Dsp Applications

As many digital signal processing (DSP) applications such as digital filtering are inherently error-tolerant, approximate computing has attracted significant attention. A multiplier is the fundamental component for DSP applications and takes up the most part of the resource utilization, namely power and area. A multiplier consists of partial product arrays (PPAs) and compressors are often used to reduce partial products (PPs) to generate the final product. Approximate computing has been studied as an innovative paradigm for reducing resource utilization for the DSP systems. In this paper, a 4:2 approximate compressor-based multiplier is studied. Approximate 4:2 compressors are designed with a practical design criterion, and an approximate multiplier that uses both truncation and the proposed compressors for PP reduction is subsequently designed. Different levels of truncation and approximate compression combination are studied for accuracy and electrical performance. A practical selection algorithm is then leveraged to identify the optimal combinations for multiplier designs with better performance in terms of both accuracy and electrical performance measurements. Two real case studies are performed, i.e., image processing and a finite impulse response (FIR) filter. The design proposed in this paper has achieved up to 16.96% and 20.81% savings on power and area with an average signal-to-noise ratio (SNR) larger than 25[Formula: see text]dB for image processing; similarly, with a decrease of 0.3[Formula: see text]dB in the output SNR, 12.22% and 30.05% savings on power and area have been achieved for an FIR filter compared to conventional multiplier designs.

scholarly journals Proposing a new variable window for better side lobe reduction

2019 ◽  
Vol 8 (9) ◽  
pp. 1107-1112
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Power Loss ◽  
Finite Impulse Response ◽  
Variable Parameter ◽  
Digital Signal ◽  
Side Lobe ◽  
Fir Filter ◽  
Side Lobe Level ◽  
Kaiser Window

Digital signal processing is most widely used to process the signal. In digital signal processing filters are used to remove some unwanted constituents from aspired signal. Windowing is a scheme of finite impulse response filters. Present paper proposes a new versatile window function. It has two variable parameters first one is window span N and another changeable parameter is r. when the value of variable parameter r increases width of major lobe of window also increases with better side lobe reduction and vice versa. Gaussian window and Kaiser window are the well-known variable windows. This paper shows that the proposed window has more desirable results in comparison of Gaussian and Kaiser window with low power loss and better side lobe reduction. To achieve minimum power loss peak side lobe level should have to minimum. Proposed window has low peak side lobe level (-17.681dB) in comparison of Gaussian (-11.836dB) and Kaiser window (-6.9704dB). Proposed work shows that the proposed window has finer spectral characteristic then Gaussian and Kaiser window. FIR filter formed by applying proposed window has narrow -3dB bandwidth (2π×0.320 rad/sample) corresponding to FIR filter formed by using Gaussian and Kaiser window. Ripple ratio of FIR filter plotted by applying proposed window (-144.321dB) is less corresponding to FIR filter delineated by using Gaussian and Kaiser which indicates that the proposed window will give better side lobe rejection and reduce the aliasing problem. In the biomedical field noise present in ECG signal can also reduce by using proposed window.

scholarly journals OPEN CORES FOR DIGITAL SIGNAL PROCESSING

2014 ◽  
Vol 25 (1) ◽  
pp. 53-62
Author(s):  
Juan Camilo Valderrama-Cuervo ◽  
Alexander López-Parrado
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Impulse Response ◽  
Finite Impulse Response ◽  
Digital Signal ◽  
Fir Filter ◽  
Hardware Verification ◽  
Infinite Impulse Response ◽  
Iir Filter ◽  
On Chip

This paper presents the design and implementation of three System-on-Chip (SoC) cores, which implement the Digital Signal Processing (DSP) functions: Finite Impulse Response (FIR) filter, Infinite Impulse Response (IIR) filter and Fast Fourier Transform (FFT). The FIR-filter core is based on the symmetrical realization form, the IIRfilter core is based on the Second Order Sections (SOS) architecture and the FFT core is based on the Radix 22 Single Delay Feedback (R22SDF) architecture. The three cores are compatible with the Wishbone SoC bus, and they were described using generic and structural VHDL. In-system hardware verification was performed by using an OpenRisc-based SoC synthesized on an Altera FPGA. Tests showed that the designed DSP cores are suitable for building SoC based on the OpenRisc processor and the Wishbone bus.

scholarly journals FPGA Implementation of Proficient 16-Tap FIR Filter Design Using Decision Tree Algorithm

2021 ◽  
Vol 12 (5) ◽  
pp. 170-180
Author(s):  
A Murali, K Hari Kishore
Keyword(s):  
Signal Processing ◽  
Filter Design ◽  
Finite Impulse Response ◽  
Digital Signal ◽  
Channel Structure ◽  
Decision Tree Algorithm ◽  
Variable Size ◽  
Structure Channel ◽  
Fir Filter Design ◽  
Dsp Applications

Lately, channel is one of the key components in signal handling applications. Among different channels, Finite Impulse Response (FIR) channel is broadly utilized in Digital Signal Processing (DSP) applications for shifting/denoising. For enormous scope coordination (VLSI) execution of fixed-coefficient FIR channels, huge asset used customary multipliers that can be acknowledged by a solitary steady multiplication (SCM) and numerous consistent augmentations (MCM) square utilizing movement and include/take away tasks. For a proficient execution, a variable size apportioning approach is proposed in direct structure channel structure that devours less zone and 11% of decrease in basic way delay, 40% decrease of all out force utilization, 15% decrease of zone delay product(ADP), 52% decrease of vitality delay product(EDP), and 42% decrease of intensity territory product(PAP), on a normal, over the cutting edge techniques. In this paper, a state choice tree calculation is proposed to decrease unpredictability in channel tap cells of variable size apportioning approach. The proposed plot creates a choice tree to perform move and expansion/deduction and aggregation dependent on the consolidated SCM/MCM approach. This plan diminishes the quantity of postpone registers required for tab cells. The proposed snake design will be actualized in Xilinx Zed, Spartan and Virtex devices and Area, power and speed investigation will be performed.

Research and Application of a FPGA-Based Dynamic Distributed Algorithm

2011 ◽  
Vol 58-60 ◽  
pp. 1696-1700
Author(s):  
Wei Zheng Ren ◽  
Ying Gao ◽  
Yan Song Cui
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Processing Speed ◽  
Distributed Algorithm ◽  
Digital Signal ◽  
Fir Filter ◽  
Effective Solution ◽  
Data Bus

A dynamic distributed algorithm (DDA) with a look-up dynamic table instead of ROM was put forward based on the theory of signed distributed algorithm, in order to improve processing speed and flexibility of product sum on FPGA. Since the DDA occupies few hardware resources, performs fast operation and realizes programmable coefficient, the limitation of digital signal processing speed on fixed data bus width and sequential operation was avoided by using the algorithm. At the same time, an effective solution to realizing coefficient programmable FIR filter was presented.

Improving the Performance and Resource Utilization of the CASPER FFT and Polyphase Filterbank

2016 ◽  
Vol 05 (04) ◽  
pp. 1641002
Author(s):  
Ryan Monroe
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Resource Utilization ◽  
Radio Astronomy ◽  
Digital Signal ◽  
Quantization Noise

The effectiveness of Digital Signal Processing (DSP) solutions for radio-astronomy is limited by the efficiency of the implemented algorithms. Novel implementations of several popular DSP algorithms are presented. Their optimization strategies are discussed and their efficiency is compared to that of the standard Collaboration for Astronomy Signal Processing and Electronics Research (CASPER) library solutions. Compared to CASPER, the PFB-FIR and FFT modules require 73% and 45% of the DSP48E1 resources, with performance dominated by ADC quantization noise for typical radio-astronomy inputs.

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