The main purpose of this paper is to focus on the design of Viterbi Decoder (VD) with low power, which is significant for receiver section of data communication applications such as Radar, Satellite, Telephone and Automatic speech recognition. The Viterbi decoder algorithm consists of three most important blocks – Branch Metric Unit (BMU), Add Compare and Select (ACS) Unit and Survivor Memory Unit (SMU). BMU computes the metrics between the input and output state transitions. ACS unit include the Path Metric Unit (PMU), which computes the metrics with the sequence to a next state of a path and selects the lower metric value as a survivor path. SMU stores the data bits which utilizes the trace back method to fetch the likelihood path from the current state to a previous state. An ACS unit is an essential block for VD. The basic recursive ACSU design consists of Ripple Carry Adder (RCA), Comparator and a Selector block, which consume more area, power and operates with high junction temperature. To overcome these drawbacks, a modified ACSU design is implemented with recursive cancellation technique. ACS unit is modified by including a trace back mechanism to obtain a low latency and high speed in VD. It is designed with low complexity multiplexers, adders, logical AND gate and comparator block. This breaking recursive ACSU design utilizes less power, high throughput, low latency and also operates at low temperature. This analysis and simulation process are accomplished using Vivado Design Suite.
Power efficient low latency survivor memory architecture for Viterbi decoder
