A constant array multiplier core generator with dynamic partial evaluation architecture selection (abstract only)

Author(s):  
Bo Yang ◽  
Nikhil Joshi ◽  
Ramesh Karri
2019 ◽  
Vol 7 (1) ◽  
pp. 24
Author(s):  
N. SURESH ◽  
K. S. SHAJI ◽  
KISHORE REDDY M. CHAITANYA ◽  
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◽  
...  

1990 ◽  
Vol 19 (3) ◽  
pp. 24-29 ◽  
Author(s):  
Li Lei ◽  
G.-H. Moll ◽  
J. Kouloumdjian

2016 ◽  
Vol 26 (03) ◽  
pp. 1730003 ◽  
Author(s):  
S. Balamurugan ◽  
P. S. Mallick

This paper provides a comprehensive review of various error compensation techniques for fixed-width multiplier design along with its applications. In this paper, we have studied different error compensation circuits and their complexities in the fixed-width multipliers. Further, we present the experimental results of error metrics, including normalized maximum absolute error [Formula: see text], normalized mean error [Formula: see text] and normalized mean-square error [Formula: see text] to evaluate the accuracy of fixed-width multipliers. This survey is intended to serve as a suitable guideline and reference for future work in fixed-width multiplier design and its related research.


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