Area Efficient Modified Array Multiplier

Multipliers are widely used for various application like signal processing. Multipliers are used for multiplication two binary data .There are different kinds of multipliers with their own advantages and disadvantages. In this paper we implemented Array multiplier which has considerably more speed but also more area, it was implemented using pseudo NMOS logic in Cadence software and the number of transistors was reduced from 2N to N+1 which also lead to reduction in area.

Efficient Implementation of Multiply Accumulate Operation Unit Using an Interlaced Partition Multiplier

A new strategy for quick multiplication of two numbers is introduced. Inputs are separated into segments, and one segment is replaced by two with zeros interlocking in each alternative segments. With zero carries between segments the product are computed, within the time needed to multiply the short partitions and add the partial sums. The multiplication of two numbers generated and adds that product to an accumulator by multiply accumulate operation (MAC unit). This operation is performed within the MAC unit. MAC is an advanced co-processor that plays a vital role in FFT, DFT, etc. The MAC unit is utilized for additional execution and its input is given to the proposed multiplier that provides a trivial speed increment over the array multiplier designs. This paper is utilized to design speed enhanced multiply Accumulate Unit by an Interlaced Partition Multiplier. This new multiplier design simulation is optimized with existing method.

Approximate Array Multipliers

This article describes the design of approximate array multipliers by making vertical or horizontal cuts in an accurate array multiplier followed by different input and output assignments within the multiplier. We consider a digital image denoising application and show how different combinations of input and output assignments in an approximate array multiplier affect the quality of the denoised images. We consider the accurate array multiplier and several approximate array multipliers for synthesis. The multipliers were described in Verilog hardware description language and synthesized by Synopsys Design Compiler using a 32/28-nm complementary metal-oxide-semiconductor technology. The results show that compared to the accurate array multiplier, one of the proposed approximate array multipliers viz. PAAM01-V7 achieves a 28% reduction in critical path delay, 75.8% reduction in power, and 64.6% reduction in area while enabling the production of a denoised image that is comparable in quality to the image denoised using the accurate array multiplier. The standard design metrics such as critical path delay, total power dissipation, and area of the accurate and approximate multipliers are given, the error parameters of the approximate array multipliers are provided, and the original image, the noisy image, and the denoised images are also depicted for comparison.

FPGA Implementation of 8-Bit Vedic Multiplier for DIT-FFT Application Using Urdhva Tiryagbhyam Sutra

This paper discusses FPGA Implementation of 8-Bit Vedic Multiplier and DIT-FFT Application Using Urdhva Tiryagbhyam Sutra. Initially 8-bit Vedic multiplier performance is compared with existing multiplier such as i) Wallace tree multiplier ii) Array multiplier iii) Booth multiplier. In this work Urdhva Tiryagbhyam (upright and across) Vedic sutra is used for multiplier design which provides better performance and consumes smaller time for computation. In this work, Modified Carry Save Adder (MCSA) is used to compute the sum of partially generated products. Further the multiplier is It reduces the computational delay towards the addition of unfinished products. The proposed design uses the Verilog HDL to develop the algorithm. The XILINX 14.7 software tool is used to simulate and synthesize the code. The proposed design is used for DIT FFT application.