Data flow graph partitioning to reduce communication cost

1986 ◽  
Author(s):  
C. Koutsougeras ◽  
C. A. Papachristou ◽  
R. R. Vemuri
Keyword(s):  
Graph Partitioning ◽  
Data Flow ◽  
Communication Cost ◽  
Data Flow Graph ◽  
Flow Graph

Data flow graph partitioning to reduce communication cost

1986 ◽  
Vol 17 (4) ◽  
pp. 82-91
Author(s):  
C. Koutsougeras ◽  
C. A. Papachristou ◽  
R. R. Vemuri
Keyword(s):  
Graph Partitioning ◽  
Data Flow ◽  
Communication Cost ◽  
Data Flow Graph ◽  
Flow Graph

scholarly journals TOGAPS: A Testability Oriented Genetic Algorithm For Pipeline Synthesis

VLSI Design ◽  
1996 ◽  
Vol 5 (1) ◽  
pp. 77-87 ◽  
Author(s):  
C. P. Ravikumar ◽  
V. Saxena
Keyword(s):  
Genetic Algorithm ◽  
Data Flow ◽  
Middle Level ◽  
Three Dimensions ◽  
Initial Population ◽  
Data Path ◽  
Data Flow Graph ◽  
Flow Graph ◽  
Mutation Operators ◽  
Average Latency

In this paper, we describe TOGAPS, a Testability-Oriented Genetic Algorithm for Pipeline Synthesis. The input to TOGAPS is an unscheduled data flow graph along with a specification of the desired pipeline latency. TOGAPS generates a register-level description of a datapath which is near-optimal in terms of area, meets the latency requirement, and is highly testable. Genetic search is employed to explore a 3-D search space, the three dimensions being the chip area, average latency, and the testability of the datapath. Testability of a design is evaluated by counting the number of self-loops in the structure graph of the data path. Each design is characterized by a four-tuple consisting of (i) the latency and schedule information, (ii) the module allocation, (iii) operation-to-module binding, and (iv) value-to-register binding. Accordingly, we maintain the population of designs in a hierarchical manner. The topmost level of this hierarchy consists of the latency and schedule information, which together characterize the timing performance of the design. The middle level of the hierarchy consists of a number of allocations for a given latency/schedule duplet. The lowest level of the hierarchy consists of a number of bindings for a specific latency/schedule/ allocation. An initial population of designs is constructed from the given data flow graph using different latency cycles whose average latency is in the specified range. Multiple scheduling heuristics are used to generate schedules for the DFG. For each of the resulting scheduled data flow graphs, we decide on an allocation of modules and registers based on a lower bound estimated using the schedule and latency information. The operation-to-module binding and the value-to-register binding are then carried out. A fitness measure is evaluated for each of the resulting data paths; this fitness measure includes one component for each of the three search dimensions. Crossover and mutation operators are used to generate new designs from the current set of parent designs. The crossover operator attempts to combine the properties of two designs. The mutation operators include addition and deletion of pure delays before scheduling, as well as changes in the register and module allocation prior to binding. The genetic algorithm applies the rule of the survival of the fittest to obtain nearoptimal solution to the otherwise intractable problem of data path synthesis. We have implemented TOGAPS on a Sun/SPARC 10 and studied its performance on a number of benchmark examples. Results indicate that TOGAPS finds area-optimal datapaths for the specified latency cycle, while reducing the number of self-loops in the data path.

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