Fault-tolerant Structures of Digital Devices Based on Boolean Complement with the Calculations Checking by Sum Codes

The article considers the construction of fault-tolerant digital devices and computing systems that does not use the principles of introducing modular redundancy. To correct the signals, a special distorted signal fixation unit, concurrent error-detection by the pre-selected redundant code circuit, as well as a signal correction block are used. The distorted signal fixation unit is implemented by the Boolean complement method, which makes it possible to design a large number of such blocks with different indicators of technical implementation complexity. When synthesizing a fault-tolerant device according to the proposed method, it is possible to organize a concurrent error-detection circuit for both the source device and the Boolean complement block in the structure of the distorted signal fixation unit. This makes it possible to choose among the variety of ways to implement fault-tolerant devices according to the proposed method, one that gives a device with the least structural redundancy. Various redundant codes can be used to organize concurrent error-detection circuits, including classical and modified sum codes. The author provides algorithms for the synthesis of distorted signal fixation unit and the Boolean complement block. The results of experimental researches with combinational benchmarks devices from the well-known LG’91 and MCNC Benchmarks sets are highlighted. The article presents the possibilities of the considered method for the organization of faulttolerant digital devices and computing systems.

Fault-Tolerant FPGA-Based Nanosatellite Balancing High-Performance and Safety for Cryptography Application

With the growth of the nano-satellites market, the usage of commercial off-the-shelf FPGAs for payload applications is also increasing. Due to the fact that these commercial devices are not radiation-tolerant, it is necessary to enhance them with fault mitigation mechanisms against Single Event Upsets (SEU). Several mechanisms such as memory scrubbing, triple modular redundancy (TMR) and Dynamic and Partial Reconfiguration (DPR), can help to detect, isolate and recover from SEU faults. In this paper, we introduce a dynamically reconfigurable platform equipped with configuration memory scrubbing and TMR mechanisms. We study their impacts when combined with DPR, providing three different execution modes: low-power, safe and high-performance mode. The fault detection mechanism permits the system to measure the radiation level and to estimate the risk of future faults. This enables the possibility of dynamically selecting the appropriate execution mode in order to adopt the best trade-off between performance and reliability. The relevance of the platform is demonstrated in a nano-satellite cryptographic application running on a Zynq UltraScale+ MPSoC device. A fault injection campaign has been performed to evaluate the impact of faulty configuration bits and to assess the efficiency of the proposed mitigation and the overall system reliability.

FPGA based Design of Triple Modular Redundancy for Hybrid Digital Pulse Width Modulation Generator

This paper proposes the Triple Modular Redundancy checker for the Hybrid Digital Pulse Width Modulation generator to verify the correctness in the output signal. The proposed design involves replicating the Hybrid Digital Pulse Width Modulation Generator thrice and the majority voter circuit validates the correct output by considering the two accurate signals out of the three outputs. The digital pulse width modulation generator is broadly classified as Counter-based Digital Pulse Width Modulation, Delay line-based Digital Pulse Width Modulation, and Hybrid-based Digital Pulse Width Modulation. Among the three methods, the Hybrid based Digital Pulse Width Modulation is preferred as the Counter-based Digital Pulse Width Modulation uses high clocking frequency and the Delay line-based Digital Pulse Width Modulation occupies a large area. The proposed Triple Modular Redundancy is implemented using the FPGA and parameters such as power analysis and device utilization chart.

Area, Power and Speed Optimized Early Output Majority Voter for Asynchronous TMR Implementation

This paper presents a new, efficient asynchronous early output majority voter that can be used to effectively realize an asynchronous triple modular redundancy (TMR) implementation. For the input-output mode asynchronous realization, the dual-rail code was used for data encoding and four phase return-to-zero and return-to-one handshake schemes were separately used for data communication. The proposed majority voter requires 62.8% less area and dissipates 37% less power on average compared to the best of the existing asynchronous majority voters while considering both handshake schemes. Importantly, the reductions in area and power are achieved without sacrificing the speed. Example TMR implementations show that the proposed majority voter leads to simultaneous reductions in cycle time, silicon area, and power dissipation. As a result, the proposed majority voter enables improved optimization in figure-of-merits such as area–cycle time product, power–cycle time product, and area–cycle time–power product for TMR implementations utilizing it compared to TMR implementations incorporating other majority voters. The circuits were implemented using a 32/28-nm CMOS technology.